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Datasheet File OCR Text:

PCI Multi-Channel Audio Controller
Revision 2.4 May 28, 2002
VIA Technologies, Inc.
Copyright Notice:
Copyright (c) 2002 VIA Technologies Incorporated. All Rights Reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. The material in this document is for information only and is subject to change without notice. VIA Technologies Incorporated reserves the right to make changes in the product design without reservation and without notice to its users.
Trademark Notices:
VT1712 and VT1724 may only be used to identify products of VIA Technologies. Windows XPTM. Windows 2000TM. Windows METM, Windows 98TM, Windows 95TM and Plug and PlayTM are registered trademarks of Microsoft Corp. PCITM is a registered trademark of the PCI Special Interest Group. All trademarks are the properties of their respective owners.
Disclaimer Notice:
No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable to the publication date of this document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change.
Offices:
USA Office: 940 Mission Court Fremont, CA 94539 USA Tel: (510) 683-3300 Fax: (510) 683-3301 or (510) 687-4654 Web: http://www.viatech.com Taipei Office: 8th Floor, No. 533 Chung-Cheng Road, Hsin-Tien Taipei, Taiwan ROC Tel: (886-2) 2218-5452 Fax: (886-2) 2218-5453 Web: http://www.via.com.tw
Ordering Information:
VT1712 - 128PQFP
Technologies, Inc. We Connect
VT1712 - PCI Multi-Channel Audio Controller
Revision History
Document Release
1.1 (engg samples) 2.0 (production)
Date
Revision
ICE1712 Data Sheet published by IC Ensemble, Inc. Reflect all the changes, including architectural ones for the production part Update Block Diag. in Fig. 4-1 Add VSR (ICE1232) support on Consumer AC-link path. CCS09_1 and _0 controls for each direction. Professional section IS clocking scheme enhancement MT01 and MT02 to support 64 and 88.2kHz. 256x and 128x MCLK global options. Appendix, Table 7-2 to reflect above. Add signal routing option of monitor to consumer section, via MT3C_0 bit (definition modified) Cleanup typos: CCI06 and CCI08 content swap location. Misc updates
Initials
RD
2.1 2.2 1/3/00
RD RD
Remove Confidential notice Update MT3B mixer volume update rate, patchbay, and digital mixer insertion delay descriptions Fix typo on power-up default PCI06; Update Fig 4-3 document converted to VIA standard data sheet format
2.3 2.4
5/24/02 IC Ensemble, Inc. bought by VIA Technologies, product part number changed to VT1712 and 5/28/02 Cleaned up typograohical errors and fixed formatting issues
DH DH
Revision 2.4, May 28, 2002
-i-
Revision History
Technologies, Inc. We Connect
VT1712 - PCI Multi-Channel Audio Controller
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii Product Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Product Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 PCI Interface and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
PCI00: Vendor Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 PCI02: Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 PCI04: PCI Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 PCI06: PCI Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 PCI08: Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 PCI0A: Class Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 PCI0C: Cache Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 PCI0D: Latency Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 PCI0E: Header Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 PCI0F: BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 PCI10: Envy24 I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 PCI14: DDMA I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 PCI18: DMA Path Registers I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 PCI1C: Multi-Track I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 PCI2C: Sub-Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 PCI34: Capability Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 PCI34: Interrupt Pin and Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Revision 2.4, May 28, 2002 -iiTable of Contents
Technologies, Inc. We Connect
VT1712 - PCI Multi-Channel Audio Controller
PCI3E: Latency and Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 PCI40: Legacy Audio Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 PCI42: Legacy Configuration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 PCI60: System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 PCI61: AC-Link Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 PCI62: I2S Converters Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 PCI63: S/PDIF Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 PCI80: Capability ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 PCI81: Next Item Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 PCI82: Power Management Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 PCI84: Power Management Control / Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 PCI86: Power Management Control / Status (PMCSR) Base and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Hardware Interfaces & Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
CCS00: Control / Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 CCS01: Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 CCS02: Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 CCS03: Envy24 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 CCS04: Envy24 Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 CCS05: NMI Status 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 CCS06: NMI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 CCS07: NMI Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 CCS08: Consumer AC'97 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 CCS09: Consumer AC'97 Command and Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 CCS0A: Consumer AC'97 Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 CCS0C: Primary MIDI UART Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 CCS0D: Primary MIDI UART Command / Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 CCS0E: NMI Status 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 CCS0F: Game Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 CCS10: I2C Port Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 CCS11: I2C Port Byte Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 CCS12: I2C Port Read / Write Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 CCS13: I2C Port Control and Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 CCS14: Consumer Record DMA Current / Base Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 CCS18: Consumer Record DMA Current / Base Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 CCS1B: PCI Configuration SERR# Shadow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 CCS1C: Secondary MIDI UART Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 CCS1D: Secondary MIDI UART Command / Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 CCS1E: Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.2 Controller Indexed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
CCI00: CCI01: CCI02: CCI03: CCI04: CCI05: Playback Terminal Count (High Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Playback Terminal Count (Low Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Playback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Playback Left Volume / Pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Playback Right Volume / Pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Soft Volume / Mute Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Revision 2.4, May 28, 2002
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VT1712 - PCI Multi-Channel Audio Controller
CCI06: CCI07: CCI08: CCI10: CCI11: CCI12: CCI20: CCI21: CCI22: CCI30: CCI31:
Playback Sampling Rate (Low Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Playback Sampling Rate (Middle Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Playback Sampling Rate (High Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Record Current / Base Terminal Count (High Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Record Current / Base Terminal Count (Low Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Record Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 GPIO Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 GPIO Write Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 GPIO Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Consumer Section Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Multi-Track Section Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.3 DDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.4 DMA Path Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4.5 Consumer Section DMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
DS0: DirectSound DMA Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 DS2: DirectSound DMA Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 DS4: Channel Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 DS8: Channel Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 Channel Control and Status at Index 4h (DS8 = x4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Consumer Mode Sampling Rate at Index 5h (DS8 = x5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Consumer Mode Left / Right Volume at Index 06h (DS8 = x6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
4.6 Professional Multi-Track Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 4.6.1
MT00: MT01: MT02: MT04: MT05: MT06:
Multi-Track Mode Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Professional Section DMA Interrupt Mask and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 Professional Section Sampling Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 Professional Section AC'97 Codec IS Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 Professional Section AC'97 Codec Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 Professional Section AC'97 Codec Command / Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 Professional Section AC'97 Codec Data Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
4.6.2
MT10: MT14: MT16: MT18:
Multi-Track Playback Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Professional Section Playback DMA Current / Base Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Professional Section Playback DMA Current / Base Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 Professional Section Playback Current / Base Terminal Count . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 Professional Section Playback and Record Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
4.6.3
MT20: MT24: MT26: MT28:
Multi-Track Record Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Professional Section Record DMA Current / Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 Professional Section Record DMA Current / Base Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 Professional Section Record Current / Base Terminal Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 Professional Section Record Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
4.6.4
Professional Section Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
MT30: Routing Control for Data to PSDOUT[0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 MT32: Routing Control for SPDOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 MT34: Captured (Recorded) Data Routing Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
4.6.5
Multi-Track Digital Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
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VT1712 - PCI Multi-Channel Audio Controller
MT38: MT3A: MT3B: MT3C: MT3E: MT3F:
Left / Right Volume Control Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 Volume Control Stream Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 Volume Control Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 Digital Mixer Monitor Routing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 Peak Meter Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42 Peak Meter Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3 AC Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
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Table of Contents
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VT1712 - PCI Multi-Channel Audio Controller
List of Figures
Figure 2-1. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 5-7. 128-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 IS Format Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 Crystals to Master Clocks Clock Generation Tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 Master Clocks to Bit Clocks, L/R Clocks and Sync Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 Multi-Track DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Data Stream Routing Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 Digital Mixer Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 Cold Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Warm Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xBCLK to xxSYNC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rise Time and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC-Link Power Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5-3 5-3 5-4 5-5 5-6 5-6
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List of Figures
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VT1712 - PCI Multi-Channel Audio Controller
List of Tables
Table 2-1. Table 2-2. Table 2-3. Table 3-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 5-2. Table 5-1. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9. Table 5-10. Table 6-1. Table A-1. Table A-2. Table A-3. Table A-4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Alphabetical Pin Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Numerical Pin Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 PCI Host Interface Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 CCSxx Controller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 DMA Channels and Respective Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 DSx Consumer DMA Channel Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 DS8 Register, Low Nibble Index Description Applicable to Channel-0 through D . . . . . . . . . . . . . . 4-21 Channel Parameter Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 MTxx Controller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cold Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Mode Master clock delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xBCLK / xxSYNC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC-Link Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-1 5-2 5-2 5-3 5-3 5-4 5-5 5-5 5-6
Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 AC-Link Interface Parameters and Ratios (Pin 50 Floating / Pulled Up) . . . . . . . . . . . . . . . . . . . . . . . IS Interface Parameters and Ratios (Pin 50 Pulled Down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S/PDIF Output IS Interface Parameters and Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S/PDIF Input IS Interface Parameters and Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A-1 A-2 A-2
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List of Tables
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VT1712 - PCI Multi-Channel Audio Controller
VT1712
Envy24TM PCI Multi-Channel Audio Controller
Product Features
* * * * * * * * * * * * * * * * * * * * * * PCI 2.1 I/F with bus mastering and burst modes 24-bit resolution audio format support Sampling rates up to 96kHz 8x2 I/O on AC-link or IS, up to 4x2 converters Simultaneous IS for S/PDIF I/O up to 96kHz 20 channels, 36-bit wide digital mixer Monitor and master copy functions Peak meters on all 20 professional multi-track streams Concurrent 16 streams DirectSoundTM accelerator Sample Rate Converter for DirectSound applications Two MPU-401 MIDI UART ports ACPI and PCI PMI support IC subset I/F for EPROM (configuration and ID storage) and peripherals control HW SoundBlaster(R) Pro legacy FM synthesis for DOS(R) legacy 64-voices SW Wavetable General MIDI Synthesizer for Windows95 DirectInputTM compatible Joystick port 8-bit GPIO port Windows(R) 95/98, NT4.0 drivers 24.576, 16.9344 or 22.5792 MHz crystal operation 3.3V operating supply (5V tolerant I/O) 128-pin PQFP (14mm x 20mm body)
1.1 Product Applications
* * * * * * * * * * PC-based multi-track audio Discrete multi-channel audio High-end PCI audio "Pro-sumer" audio General purpose multi-channel I/O Computer telephony PC-based data acquisition PC-based waveform generation PC-based instrumentation PC-based control and automation
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Features and Overview
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VT1712 - PCI Multi-Channel Audio Controller
Overview
The Envy24TM is a versatile PCI multi-channel I/O controller. It allows up to 12x2 simultaneous input and output channels with the data source or destination being either analog or digital. Some of the typical applications for this part are computer based multi-track audio, multi-channel audio, PC-based data acquisition, waveform generation and computer telephony integration. The Envy24 can be combined with professional grade IS converters, S/PDIF transmitters/receivers or AC-link codecs, such as the VT1611ATM. The controller integrates a very high resolution digital mixer allowing up to 20 channels of mixing. This is aimed specifically for monitoring final outputs, making master copies and for budget conscious studios that may lack an individual out-board mixer. The Envy24 supplies a master IC interface providing connection to an EPROM to store and retrieve PCI Subsystem and Subsystem vendor IDs, specific board configurations and custom features identification. This interface is available for controlling other devices as well. For target markets where legacy audio is still important, the SoundBlaster Pro compatible hardware ensures hardware compatibility under DOS for DDMA (Distributed DMA) and non-DDMA systems. The device also includes a Microsoft Win9x architecture based DirectSound hardware accelerator that interfaces to AC'97 via AC-link. The separate path allows concurrent operation with the 24-bit professional multi-track audio section. The Envy24 is a "Digital-Ready" audio device allowing acceleration in cooperation with the host and redirecting audio streams to other endpoints. The Envy24 integrates two independent MPU-401 MIDI UARTs. This features allows hooking up multiple external MIDI devices and dedicating the two paths for different purposes. Additionally, a conventional standard Joystick port and timer is integrated. Only R and C components are necessary to complete the circuit. Also an 8-bit GPIO brings flexibility for multi-purpose use. The Envy24 is a power miser device due to its aggressive power management scheme and hard-wired design architecture. The device is ACPI compliant making it suitable for platforms designed for "OnNow". Depending on the sampling rates that need to be supported by the target solution, one or two crystals are sufficient to operate the whole system. Alternatively, a PLL Clock synthesizer chip can be used to generate the necessary frequencies. The clock chip can be controlled by the GPIO pins for programmability. For more detail on the part, please refer to the system block diagram Figure 4-1 in Section 4.
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Features and Overview
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VT1712 - PCI Multi-Channel Audio Controller
Pinouts
The following section includes the pinout diagram of the chip that is housed in a standard 128-PQFP. Also, three lists of pin assignments are provided for your convenience. They are logically sorted by functionality and description, alphabetically and numerically sorted in ascending order. These list are provided to assist hardware development, test, debugging and quality assurance. The mechanical data about the part can be found in Section 6.
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Pinouts
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VT1712 - PCI Multi-Channel Audio Controller
2.1 Pinout Diagram
JSD1 JSD0 PRST# SPDOUT SPDIN GND SPSYNC SPSCLK SPMCLKIN SPMCLKOUT INTA# RST# VCC GND PCICLK GNT# REQ# AD31 AD30 VCC AD29 AD28 AD27 AD26 AD25 GND 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
VCC AD24 CBE3# IDSEL AD23 AD22 GND AD21 AD20 AD19 AD18 AD17 VCC GND AD16 CBE2# FRAME# IRDY# TRDY# GND DEVSEL# STOP# SERR# PAR CBE1# GND VCC AD15 AD14 AD13 AD12 AD11 GND AD10 AD9 AD8 CBE0# VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 GND_X1 VCC_X2 XOUT2 XIN2 GND_X2 GPIO7/RX2 GPIO6/TX2 GPIO5 GPIO4 GND VCC GPIO3 GPIO2 GPIO1 GPIO0 AD0 AD1 AD2 GND VCC AD3 AD4 AD5 AD6 AD7 GND
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
JSD2 JSD3 GND JSD4 JSD5 JSD6 JSD7 TX1 RX1 VCC CMCLK CSDOUT CBCLK CSDIN CSYNC GND CRST# PMCLK PSDOUT[3] PSDOUT[2] PSDOUT[1] VCC GND PSDOUT[0] PBCLK PSDIN[3] PSDIN[2] PSDIN[1] GND PSDIN[0] PSYNC SCLK SDA TESTEN# NC VCC_X1 XOUT1 XIN1
Figure 2-1. 128-Pin PQFP Package
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VT1712 - PCI Multi-Channel Audio Controller
2.2 Pin Descriptions
The following table provides a brief description of each pin of the VT1712. Pins with dual usage may be listed twice for consistency. The following abbreviations are used to identify the pin types. I - Input Signal O - Output Signal B - Bidirectional Signal OD - Open Drain A - Analog Signal PU - Pull-up. 50 K nominal Table 2-1. Pin Descriptions
PCI Bus Interface
Symbol
AD[31:0] CBE#[3:0] PCICLK DEVSEL# FRAME# GNT# IDSEL INTA# IRDY# PAR REQ# RST# SERR# STOP# TRDY#
Type
B B I B B I I OD B B O I OD B B
Description
Multiplexed PCI Address / Data Bus. Bus Command / Byte Lane Enable. These signals are bus commands during the address phase and byte lane enable during the data phase. These signals are output during a bus master cycle. PCI Bus Clock. Device Select. The VT1712 drives this signal active when it decodes its address as the current target of the current acces. PCI Cycle Frame. When asserted by the bus mster, this signal indicates the beginning of a bus transaction.During the final data phase of a bus transaction it is deasserted. PCI Bus Grant. When active it indicates bus master is granted to VT1712. Initialization Device Select. This is the chip select during the PCI configuration register accesses PCI Interrupt Request. Initiator Ready. Parity Signal. Bus Master Control Request System Reset. All VT1712 registers and state machines are at default when this signal is asserted. PCI System Error. Target Disconnect. Target Ready. IC Port
SDA SCLK
B O
Serial Data. Serial Bit Shift Clock. Game Port
JSD[7:4] JSD[3:0]
I A
Joystick Fire Buttons. Joystick Coordinates Inputs. Primary MPU-401 UART
TX1 RX1
O, PU I, PU
Primary MPU-401 Transmit Data. Primary MPU-401 Receive Data.
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VT1712 - PCI Multi-Channel Audio Controller
Table 2-1. Pin Descriptions (continued)
Secondary MPU-401 UART TX2 / GPIO6 RX2 / GPIO7 O I Secondary MPU-401 Transmit Data. Secondary MPU-401 Receive Data. Consumer AC-Link Interface CSYNC CBCLK CSDIN CSDOUT CMCLK CRST# O I I O O O 48kHz fixed rate sync pulse 12.288MHz Serial Bit Clock Incoming Serial Data Stream Outbound Serial Data Stream Master Clock for AC'97 codec. Outputs XIN1 crystal frequency, typically 24.576 MHz . Consumer Codec master reset Professional Multi-Track AC-Link / IS Interface PSYNC PBCLK PSDIN[3:0] PSDOUT[3:0] PMCLK PRST# O I/O I O O O AC'97: 48kHz fixed rate sync pulse for up to 4 codecs, or 8 IS type converters: Left/Right Clock Serial Bit Clock. It can be master or slave configured 4 separate incoming stereo stream pairs 4 separate outbound stereo stream pairs Master Clock for AC'97 codecs or IS converters Cold reset for Professional Multi-track IS/AC-link I/F Clocks XOUT1 XIN1 XOUT2 XIN2 A A A A Clock Out 1. Clock In 1. 24.576 MHz (512*48 KHz). Runs all fixed clock blocks. Clock Out 2. Clock In 2. 16.9344 MHz (384*44.1 KHz) or 22.5792 MHz (512*44.1 KHz) or external PLL output S/PDIF (Sony / Philips Digital Interface) SPMCLKIN SPMCLKOUT SPSCLK SPDIN SPDOUT SPSYNC I O O I O O S/PDIF Master Clock Input. S/PDIF Master Clock Output. S/PDIF Serial Bit Clock. Incoming S/PDIF Serial Data. Outbound S/PDIF Serial Data. S/PDIF Frame Sync. General Purpose I/O
Symbol
GPIO7 / RX2 GPIO6 / TX2 GPIO5 / S1 GPIO4 / S0 GPIO3 / EPROM
Type
B, PU B, PU B, PU B, PU B, PU
Description
General Purpose I/O. Secondary MPU-401 Receive data General Purpose I/O. Secondary MPU-401 Transmit data General Purpose I/O. Clock rate select for external clock chip select General Purpose I/O. Clock rate select for external clock chip select General Purpose I/O. EPROM presence indicator during power-up (default). The state is reflected on CCS13[7] bit.
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VT1712 - PCI Multi-Channel Audio Controller
Table 2-1. Pin Descriptions (continued)
GPIO2 GPIO1 GPIO0 / IS# B, PU B, PU B, PU General Purpose I/O. General Purpose I/O. General Purpose I/O. Sets AC-link interface for professional section during power-up (default). The state is reflected on PCI61[7] bit in reverse polarity. Test Mode TESTEN# I, PU Test Mode Enable. Do not connect for normal operation. Power and Ground VCC GND Digital Supply Voltage. 3.3V Ground.
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VT1712 - PCI Multi-Channel Audio Controller
2.3 Pin Lists
Table 2-2 lists all the pins alphabetically. Table 2-3 lists all the pins in numerical order.
Table 2-2. Alphabetical Pin Listing
Symbol
AD[31:0] CBCLK CBE#[3:0] CMCLK CRST# CSDIN CSDOUT CSYNC DEVSEL# FRAME# GND GND_X1 GND_X2 GNT# GPIO[0] / IS# GPIO[1] GPIO[2] GPIO[3] / EPROM GPIO[4]/S0 GPIO[5]/S1 GPIO[6] / TX2 GPIO[7] / RX2 IDSEL INTA# IRDY# JSD[7:0] PAR PBCLK PCICLK
Pin(s)
2, 5-6, 8-12, 15, 28-32, 34-36, 40-44, 47-49, 120-121, 123-127, 90 3, 16, 25, 37 92 86 89 91 88 21 17 7, 14,20, 26, 33, 39, 46, 55, 74, 80, 87, 100, 108, 116, 128 64 60 118 50 51 52 53 56 57 58 59 4 113 19 96-99, 101-104 24 78 117
Symbol
PMCLK PRST# PSDIN[3:0] PSDOUT[3:0] PSYNC REQ# RST# RX1 RX2 / GPIO[7] SCLK SDA SPDIN SPDOUT SERR# SPMCLKIN SPMCLKOUT SPSCLK SPSYNC STOP# TESTEN# TRDY# TX1 TX2 / GPIO[6] VCC VCC_X1 VCC_X2 XIN[2:1] XOUT[2:1]
Pin(s)
85 105 73, 75-77 79, 82-84 72 119 114 94 59 71 70 107 106 23 111 112 110 109 22 69 19 95 58 1, 13, 27, 38, 45, 54, 81, 115, 122 67 63 61, 65 62, 66
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Table 2-3. Numerical Pin Listing
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Symbol
VCC AD24 CBE3# IDSEL AD23 AD22 GND AD21 AD20 AD19 AD18 AD17 VCC GND AD16 CBE2# FRAME# IRDY# TRDY# GND DEVSEL# STOP# SERR# PAR CBE1# GND VCC AD15 AD14 AD13 AD12 AD11
Pin #
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol
GND AD10 AD9 AD8 CBE0# VCC GND AD7 AD6 AD5 AD4 AD3 VCC GND AD2 AD1 AD0 GPIO[0] GPIO[1] GPIO[2] GPIO[3] VCC GPIO[4] / S0 GPIO[5] / S1 GPIO[6] / TX2 GPIO[7] / RX2 GND_X2 XIN2 XOUT2 VCC_X2 GND_X1 XIN1
Pin #
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
Symbol
XOUT1 VCC_X1 VCC GND TESTEN# SDA SCLK PSYNC PSDIN[0] GND PSDIN[1] PSDIN[2] PSDIN[3] PBCLK PSDOUT[0] GND VCC PSDOUT[1] PSDOUT[2] PSDOUT[3] PMCLK CRST# GND CSYNC CSDIN CBCLK CSDOUT CMCLK VCC RX1 TX1 JSD7
Pin #
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Symbol
JSD6 JSD5 JSD4 GND JSD3 JSD2 JSD1 JSD0 TX2 SPDOUT SPDIN VCC SPSYNC SPSCLK SPMCLKIN SPMCLKOUT INTA# RST# VCC GND PCICLK GNT# REQ# AD31 AD30 VCC AD29 AD28 AD27 AD26 AD25 GND
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PCI Interface and Configuration Registers
Table 3-1. PCI Host Interface Register Map
Byte 3 Byte 2
Device Identification PCI Device Status Class Code BIST Header Type
Byte 1
Byte 0
Vendor Identification PCI Command
Offset (Hex)
00 04 08 0C 10 14 18 1C 2C 30 34 38
Reserved. Read as 0 Latency Timer
Revision ID Reserved. Read as 0
Controller I/O Base Address DDMA I/O Base Address DMA Path Registers I/O Base Address Professional Multi-Track I/O Base Address Subsystem ID Reserved. Read as 0 Capability Pointer Reserved. Read as 0 Minimum Latency and Maximum Grant Legacy Configuration Control Interrupt Pin and Line Legacy Audio Control Subsystem Vendor ID
3C 40 60
Hardware Configuration Control Power Management Capability PMCSR Support Extensions and Data Next Item Pointer Capability ID
80 84
Power Management Control and Status
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3.1 PCI Configuration Registers
PCI00: Vendor Identification Address Offset: 00 - 01h Default Value: 1412h
Bit
15:0
Attribute
RO
Description
Vendor Identification Number. 16-bit value assigned to VIA Technologies, Inc.
PCI02: Device Identification Address Offset: 02 - 03h Default Value: 1712h
Bit
15:0
Attribute
RO
Description
Device Identification Number. 1712 reflects the part number.
PCI04: PCI Command Address Offset: 04 - 05h Default Value: 0000h
Bit
15:10 9 8 7 6 5 4 3 2 1 0
Attribute
R0b R0b R/W R0b R0b R0b R0b R0b R/W R0b R/W
Description
Reserved. Read as 0s. Fast Back-to-Back Enable. This bit is hardwired to 0 (Not Implemented). SERR# enable. 1= enable. 0=disable (default).When enabled, FM and MIDI I/O writes will be trapped and causes SERR# asserted. PCISTS register reports the status of the SERR# signal.This bit has a shadow defined in register bit CCS1B_0. A/D stepping enable. This bit is hardwired to 0 (Not Implemented). Parity error detect enable. Hardwired to 0 (Not Implemented). VGA palette snoop enable. Hardwired to 0 (Not Implemented). Memory write and invalidate enable. Hardwired to 0 (Not Implemented). Special Cycle Enable (SCE). Hardwired to 0 (Not Implemented). Bus master enable. 1=enable. 0=disable (default). Memory Access. Hardwired to 0 (Not Implemented). I/O Space accesses enable. 1=enable. 0=disable (default).
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PCI06: PCI Status Address Offset: 06 - 07h Default Value: 0210h
Bit
15 14 13 12 11 10:9 8 7 6 5 4 3:0
Attribute
R/W/C R/W/C R/W/C R/W/C R0b R10b R0b R0b R0b R0b R1b R0000b
Description
PAR status. Parity error detected (even when parity not enabled). SERR# status. This bit is set to 1 when SERR# is asserted (even when it is not enabled) and cleared by writing 1 to it. Master abort status. This bit is set to 1 when master aborts and cleared by writing "1" to it. Received target abort status. This bit is set to 1 when target abort is received and cleared by writing a 1 to it. Signaled target abort status. This bit is set when target abort generated and cleared by writing a 1 to it. Hardwired to 0 (never abort). DEVSEL# timing status. Envy24 always asserts DEVSEL# with medium timing. PERR# response. Read as 0 (Not Implemented). Fast back to back. Read as 0 (Not implemented). User Define Function (UDF). Read as 0 (Not implemented). Reserved. Read as 0. 33MHz only. Hardwired to 1 to indicate the support for PCI power management capability. Reserved. Read as 0s.
PCI08: Revision ID Address Offset: 08h - 09h Default Value: 000Xh
Bit
15:0 7:0
Attribute
R00h RO
Description
Revision ID
PCI0A: Class Code Address Offset: 0Ah - 0Bh Default Value: 0401h
Bit
15:8 7:0
Attribute
RO RO
Description
Base Class. Reflects Multimedia Sub class. Reflects Audio.
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PCI0C: Cache Size Address Offset: 0Ch Default Value: 00h
Bit
7:0
Attribute
RO
Description
Read as 0. Not supported
PCI0D: Latency Timer Address Offset: 0Dh Default Value: 00h
Bit
7:3 2:0
Attribute
R/W RO
Description
Latency timer Read as 0
PCI0E: Header Type Address Offset: 0Eh Default Value: 00h
Bit
7:0
Attribute
RO
Description
Read as 0
PCI0F: BIST Address Offset: 0Fh Default Value: 00h
Bit
7:0
Attribute
RO
Description
Read as 0. Not supported
PCI10: Envy24 I/O Base Address Offset: 10h - 13h Default Value: 00000001h
Bit
31:5 4:1 0
Attribute
RW R0h R1b
Description
Controller I/O Base Address for CCSxx registers described in section 4.1 Hardwired to 0 to have 32 bytes I/O space. This includes UARTs and game port. Hardwired to 1 to indicate registers map to I/O space
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PCI14: DDMA I/O Base Address Offset: 14h -17h Default Value: 00000001h
Bit
31:4 3:1 0
Attribute
R/W R000b R1b
Description
DDMA Slave Channel Base Address for DDMAx registers described in section 4.2 Hardwired to 0 to have 16 bytes I/O space Hardwired to 1 to indicate registers map to I/O space
PCI18: DMA Path Registers I/O Base Address Offset: 18h - 1Bh Default Value: 00000001h
Bit
31:4 3:1 0
Attribute
R/W R000b R1b
Description
DMA path registers I/O Base Address for DSx registers described in section 4.4 Hardwired to 0 to specify requirement of 16 bytes I/O space Hardwired to 1 to indicate registers map to I/O space
PCI1C: Multi-Track I/O Base Address Offset: 1Ch - 1Fh Default Value: 00000001h
Bit
31:6 5:1 0
Attribute
R/W R0 R1b
Description
Multi-Track I/O Base Address for MTxx registers described in section 4.5 Hardwired to 0 to have 64 bytes I/O space Hardwired to 1 to indicate registers map to I/O space
PCI2C: Sub-Vendor ID Address Offset: 2Ch - 2Fh Default Value: 17121412h
Bit
31:0
Attribute
RO
Description
Sub-vendor ID: Read it from external EPROM after reset if it exists, otherwise, same as vendor ID. It can also be written by disabling write protection bit defined in PCI42_7.
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PCI34: Capability Pointer Address Offset: 34h Default Value: 80h
Bit
7:0
Attribute
RO
Description
CP7-CP0: Capability data structure pointer for PCI power management. Hardwired to 80h.
PCI34: Interrupt Pin and Line Address Offset: 3Ch - 3Dh Default Value: 01FFh
Bit
15:8 7:0
Attribute
RO R/W
Description
01h read from this register indicates the interrupt pin used is INTA# and cannot be modified. Interrupt line routing information set by POST during power-up initialization. Default FFh indicates no connection to the PIC yet.
PCI3E: Latency and Grant Address Offset: 3Eh - 3Fh Default Value: 0000h
Bit
15:8 7:0
Attribute
RO RO
Description
Maximum latency Minimum grant
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PCI40: Legacy Audio Control Address Offset: 40h - 41h Default Value: 807Fh
Bit
15 14:12 11:10 9:8
Attribute
R/W R000b R/W R/W
Description
0: Legacy Audio Hardware enable. 1: Legacy Audio Hardware disabled (default) Reserved Reserved SB DMA Channel Select: 00 DMA 0 01 DMA 1 (default) 10 Reserved 11 DMA 3 I/O Address Alias Control 1: select the 10-bit decode (default) 0: select the 16-bit decode In either case, the AD(31:16) should be zero Reserved MPU-401 I/O enable Game Port enable (200h) FM I/O enable (AdLib 388h base) SB I/O enable
7:6
R/W
5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W
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PCI42: Legacy Configuration Control Address Offset: 42h - 43h Default Value: 0006h
Bit
15:8 7 6 5 4 3
Attribute
R/W R/W R/W R/W R/W R/W
Description
Interrupt vector to be snooped. 0: SVID read only. (default) 1: SVID read/write enable. 0: snoop SB 22C/24Ch I/O write cycle to assert SERR#: disable (default) 1: snoop SB 22C/24Ch I/O write cycle to assert SERR# : enable 0: snoop PIC I/O R/W cycle to assert SERR#: disable (default) 1: snoop PIC I/O R/W cycle to assert SERR#: enable 0: snoop PCI bus interrupt acknowledge cycle: disable (default) 1: snoop PCI bus interrupt acknowledge cycle: enable 0: SB base 220h (default) 1: SB base 240h 0: MPU-401 base 300h 1: MPU-401 base 310h 2: MPU-401 base 320h 3: MPU-401 base 330h (default) 0: DDMA enable (default) 1: Legacy DMA enable
2:1
R/W
0
RW
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PCI60: System Configuration Address Offset: 60h Default Value: 0Fh The following four bytes (60h-63h) should be read from E2PROM by driver and then written to setup the codec configuration, unless otherwise noted.
Bit Attribute Description
XIN2 Clock Source Configuration. Refer to register MT01 and Table A-2 in the Appendix 00: XIN2: 22.5792MHz crystal (44.1kHz*512) 01: XIN2: 16.9344MHz crystal (44.1kHz*384) 10: XIN2: from external clock synthesizer chip (e.g. MK1412) which needs to be controlled via S0, S1 pins. These shared GPIO4 and 5 pins become write only and the direction will not be controllable via CCI22. 11: - Reserved 0: one MPU-401 UART only 1: two MPU-401 UARTs. Consumer AC'97 codec: 0: Consumer AC'97 does exist 1: Consumer AC'97 does not exist Must have at least one pair of professional multi-track ADC and DAC. 00: one stereo ADC connected 01: two stereo ADCs connected 10: three stereo ADCs connected 11: four stereo ADCs connected Must have at least one pair of professional multi-track ADC and DAC. 00: one stereo DAC connected 01: two stereo DACs connected 10: three stereo DACs connected 11: four stereo DACs connected
7:6
R/W
5
R/W
4
R/W
3:2
R/W
1:0
R/W
PCI61: AC-Link Configuration Address Offset: 61h Default Value: 00h Except for bit 7, the four bytes at 60h-63h should be read from E2PROM by driver and then written to setup the codec configuration.
Bit
7 6:2 1
Attribute
R/W R/W R/W
Description
Multi-track converter type: 0: AC'97 1: IS. Reflects power-up status of pin 50 during reset cycle in reverse polarity. Can be overwritten Reserved. If bit 7 is 0: 0: split mode: AC'97 codec SDATA_OUT split to different pin outputs 1: packed mode: AC'97 codec SDATA_OUT packed in slots 3 to 10 If bit 7 is 0: 0: split mode: AC'97 code:SDATA_IN split from different pin inputs 1: packed mode: AC'97 codec SDATA_IN packed in slots 3 to 10
0
R/W
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PCI62: I2S Converters Features Address Offset: 62h Default Value: 01h This byte is valid only when PCI61_7 is 1. The four bytes at 60h-63h should be read from E2PROM by driver and then written to setup the codec configuration.
Bit
7 6
Attribute
R/W R/W
Description
For IS codec Volume and mute 0: IS codec has no volume/mute control feature. 1: IS codec has volume/mute control capability and need to be program through GPIO (e.g., CS4222) IS converter 96kHz sampling rate support. 0: does not; 1 : supports Converter resolution: 00: 16-bit 01: 18-bit 10: 20-bit 11: 24-bit Other IS IDs
5:4
R/W
3:0
R/W
PCI63: S/PDIF Configuration Address Offset: 63h Default Value: 03h The four bytes at 60h-63h should be read from E2PROM by driver and then written to setup the codec configuration.
Bit
7:2 1 0
Attribute
R/W R/W R/W
Description
S/PDIF chip ID 1: S/PDIF Stereo In is present. Forces 64bpf on IS interface. 1: S/PDIF Stereo Out is present. Forces 64bpf on IS interface.
PCI80: Capability ID Address Offset: 80h Default Value: 01h
Bit
7:0
Attribute
RO
Description
Capability ID
PCI81: Next Item Pointer
Address Offset: 81h Default Value: 00h
Bit
7:0
Attribute
RO
Description
Hardwired to 0 to indicate the end of list
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PCI82: Power Management Capabilities Address Offset: 82h - 83h Default Value: 0401h
Bit
15:11 10 9 8:6 5 4 3 2:0
Attribute
RO R1 R0 R000 R0 R0 R0 R001b
Description
PME not supported. Hardwired to 0. D2 state support. Hardwire to 1. D1 state not support. Hardwired to 0. Reserved. DSI. Hardwired to 0. Aux. Power. Hardwired to 0 PMC clock for generation of PME#. Hardwired to 0. Hardwired to 001 to indicate PPMI 1.0 compliance
PCI84: Power Management Control / Status Address Offset: 84h - 85h Default Value: 0000h
Bit
15 14:13 12:9 8 7:2
Attribute
R0b R00b R0h R0b RO
Description
PME status. Read as 0. Data scale. Not supported. Data select: Not supported. PME assertion. Hardwired to 0 Hardwired to 000000 Power state. To determine the current state of power state. 00 : D0 01 : D1 (not supported) 10 : D2 11 : D3_hot
1:0
R/W
PCI86: Power Management Control / Status (PMCSR) Base and Data Address Offset: 86h - 87h Default Value: 0000h
Bit
15:0
Attribute
R0000h
Description
-
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Hardware Interfaces & Interface Registers
In the previous section PCI host interface and configuration registers were discussed. In this section description of the major blocks, their respective hardware interfaces and associated registers will be discussed. In most cases the four I/O base addresses have a one to one correspondence with the major functional blocks. Therefore, the following subchapters will be organized based on the logical grouping of the registers on the offsets of their respective I/O base addresses. The first figure in this section, Figure 4-4-1, is a chip level block diagram with typical external interface usage. It is a very good overview of the whole chip, but should not be regarded as the most detailed diagram. As appropriate, the databook will resort to sub-block diagrams to further detail the functionality. These are the multi-track DMA transfer mechanism, data stream routing capabilities and the digital mixer block diagram.
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4 DAC/Codec S/PDIF I/O
4 ADC/Codec
AC'97 Codec
Four I2S or AC-Link Pairs
I2S I/O
Four I2S or AC-Link Pairs
AC-Link I/F
12x24b ch.
20 Ch., 36b Digital Mixer
2x20b ch. 2x16b ch.
16 ch. SRC and DS Digital Mixer
10x24b ch. 10x24b ch.
DMA
12x24b ch.
RX1 TX1
RX2 TX2
SD
GPIO
JSD
VT1712 - PCI Multi-Channel Audio Controller
DMA
DirectSound DMA
Legacy and PCM Audio
Record DMA
MPU-401 UART
MPU-401 UART
IC/EPROM PORT
8-bit GPIO
Joystick Port
14 str.
8/16b
packed path
PCI 2.1 Bus Master BIU with Burst Mode
PCI BUS
Figure 4-1. Functional Block Diagram
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4.1 Controller Registers
The following registers are offset from base address set by PCI10. The 32 bytes I/O space includes main control / status registers, I2C interface, MPU-401 MIDI UARTs and game port control as well. Each CCSxx register is physically located at the address determined by [PCI10]+xx and accessed directly. The registers can be accessed as a byte, word or dword register. Table 4-2. CCSxx Controller Register Map
Byte 3
CCIxx Index NMI Index
Byte 2
Envy24 Status NMI Data
Byte 1
Interrupt Mask NMI Status 1 C. AC `97 Comm./Stat. MIDI 1 Comm./Status IC Port Byte Address
Byte 0
Envy24 Control/Stat. CCIxx Data Cons. AC `97 Index MIDI UART 1 Data IC Port Dev. Address
Offset (Hex)
00 04 08 0C 10 14 18 1C
Consumer AC `97 Data Port Game Port IC Port Control/Status NMI Status 2 IC Port R/W Data
Consumer Record DMA Current/Base Address SERR# Shadow Timer Consumer Record DMA Count Address MIDI 2 Comm./Status MIDI UART 2 Data
CCS00: Control / Status Address Offset: 00h Default Value: 00h
Bit
7 6
Attribute
R/W R/W
Description
Entire Chip soft reset Legacy mode only: 1: enable SERR# assertion for the DS DMA Channel-C interrupt 0: disable SERR# assertion for the DS DMA Channel-C interrupt (default)
5 4
RO R/W Legacy mode only: 1: set the DOS WT volume control coming from DS Channel-C/D index registers B. 0: set the DOS FM volume control coming from SB mixer register space. (default) This bit is used in the legacy mode for the switching between FM and WT under DOS. For FM and WT under Windows, it is always coming from DS Channel-C/D index register B. 0: SERR# level (default) 1: SERR# edge (only one PCI clock width) Legacy mode only: 1: enable SERR# assertion for SB interrupt 0: disable SERR# assertion for SB interrupt (default) Mode select: 0: SB mode 1: native mode
3 2 1
R/W R0 R/W
0
R/W
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CCS01: Interrupt Mask Address Offset: 01h Default Value: FEh
Bit
7 6 5 4 3 2 1 0
Attribute
R/W R/W R/W R/W R/W R/W R/W R/W
Description
Primary MIDI interrupt mask Timer mask Secondary MIDI interrupt mask. Professional Multi-track playback and record. This is the macro interrupt mask for both playback and record. FM/MIDI trapping interrupt mask Playback DS DMA channels mask (effective for all the playback DMA channels from 0 to D) Consumer record DMA channel interrupt mask Consumer/SB mode playback interrupt mask (DMA channel E and F)
CCS02: Interrupt Status Address Offset: 02h Default Value: 00h. These bits are sticky and only writing a 1 to that bit location will clear itself.
Bit
7 6 5 4 3 2 1 0
Attribute
R/W/C R/W/C R/W/C RO R/W/C RO R/W/C R/W/C
Description
Primary MIDI receiver FIFO Timer Secondary MIDI receiver FIFO Multi-track playback or record. This is the macro interrupt status for both playback and record. To clear individual status bit, write a 1 to the associated bit location defined in section 4.4. FM/MIDI trapping Direct Sound. This is the macro interrupt status for DS Channels (0 through D). To clear individual status bit, Write a 1 to the associated bit location defined in the DS DMA channel register section. Native mode record (Record DMA) Native/SB playback
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CCS03: Envy24 Index Address Offset: 03h Default Value: 00h
Bit
7:6 5:0
Attribute
R00b R/W
Description
Index register. Write the CCIxx register's xx index as described in section 4.1.1.
CCS04: Envy24 Data Address Offset: 04h Default Value: 00h.
Bit
7:0
Attribute
See 4.1.1
Description
Data register. Content for CCIxx register.
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CCS05: NMI Status 1 Address Offset: 05h Default Value: 00h Description: This register pertains to legacy audio hardware synthesis emulation in DOS. Reading from this register will clear itself and de-assert the SERR# signal. However, it will not clear the SERR# bit PCI06[14]. To clear it, write 1 to that bit location instead. Refer to register CCS0E as well.
Bit
7 6 5 4 3 2 1 0
Attribute
RO RO R0b RO RO RO R0 RO
Description
1: PCI I/O read/write cycle if bit PCI43[5] is set to 1. 1: SB 22C/24C write if bit PCI 43[6] is set to 1. 1: SB interrupt (either SB DMA or SB F2 command) if bit [PCI10][1] is set to 1. 1: DS channel C DMA interrupt (for FM/WT data transfer DMA) if bit [PCI10][6] is set to 1. 1: MIDI 330h or [PCI_10]h+Ch write 1: FM data register write (389h/221h/229h/38bh/223h)
CCS06: NMI Data Address Offset: 06h Default Value: 00h Description: This register pertains to legacy audio hardware synthesis emulation in DOS.
Bit
7:0
Attribute
RO
Description
Trapped data for TSR to be read (either FM 389h(221h,229h)/38bh(223h), MIDI 330h write, PIC I/O or SB 22C/ 24C write cycle (if enabled). Note that only write to FM data will assert SERR# but not write to FM index.
CCS07: NMI Index Address Offset: 07h Default Value: 00h Description: This register pertains to legacy audio hardware synthesis emulation in DOS.
Bit
7:0
Attribute
RO
Description
Trapped data for FM Index only.
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CCS08: Consumer AC'97 Index Address Offset: 08h Default Value: 00h
Bit
7 6:0
Attribute
R0b R/W
Description
AC'97 registers Index. Refer to the AC'97 specification for register descriptions.
CCS09: Consumer AC'97 Command and Status Address Offset: 09h Default Value: 00h
Bit
7 6 5 4 3 2 1 0
Attribute
R/W R/W R/W R/W RO R0b R/W R/W
Description
Cold reset W: 1 to cold reset the codec. 0: CRST# will be de-asserted. Warm reset W: 1 to warm reset the codec by asserting CSYNC. 0: CSYNC will be de-asserted. W: 1 to write to AC'97 codec registers R: 1 indicate the write cycle is still in progress. Cleared when write cycle is complete. W: 1 to read from AC'97 codec registers R: 1 indicate the read cycle is still in progress. This bit is cleared when there is valid data. AC'97 codec ready status bit. After power on, driver should check that this bit is 1 before accessing codec registers. Enable VSR for Playback (DirectSound accelerator bypassed. Only Channel-E and F active) Enable VSR for Record (digital return feature automatically disabled)
CCS0A: Consumer AC'97 Data Port Address Offset: 0Ah - 0Bh Default Value: 0000h
Bit
15:8 7:0
Attribute
R/W R/W
Description
AC'97 codec register data higher byte (index 0Bh) AC'97 codec register data lower byte (index 0Ah)
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CCS0C: Primary MIDI UART Data Address Offset: 0Ch Default Value: 00h
Bit
7:0
Attribute
R/W
Description
MIDI UART data register
CCS0D: Primary MIDI UART Command / Status Address Offset: 0Dh Default Value: 00h
Bit
7:0
Attribute
R/W
Description
MIDI UART command and status register
CCS0E: NMI Status 2 Address Offset: 0Eh Default Value: 00h Description: This register pertains to legacy audio hardware synthesis emulation in DOS. Reading from this register will not clear itself. Refer to register CCS05 as well
Bit
7:6 5:4 3:0
Attribute
R0 RO RO
Description
FM bank indicator: 01: FM bank 0 (388h/220h/228h) 10: FM bank 1 (38ah/222h) PIC I/O cycle 0001: 20h write 0010: A0h write 0101: 21h write 0110: A1h write 1001: 20h read 1010: A0h read 1101: 21h read 1110: A1h read
CCS0F: Game Port Address Offset: 0Fh Default Value: 00h
Bit
7:0
Attribute
RW
Description
Game port register
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CCS10: I2C Port Device Address Address Offset: 10h Default Value: 00h Each write to this register will trigger to start the read/write cycle. So, before write to this I/O address, driver needs to check to make sure that the status bit is idle as defined in the IC status register CCS13. The controller is always the only master and does not support multi-byte data burst mode.
Bit
7:1
Attribute
R/W
Description
I2C device address. Device address "1010000" is reserved for the external IC E2PROM such as 24C02 for sub-vendor ID and configuration data. 0: read 1: write
0
R/W
CCS11: I2C Port Byte Address Address Offset: 11h Default Value: 00h
Bit
7:0
Attribute
R/W
Description
Byte address to read or write
CCS12: I2C Port Read / Write Data Address Offset: 12h Default Value: 00h
Bit
7:0
Attribute
RW
Description
Read or write data
CCS13: I2C Port Control and Status Address Offset: 13h Default Value: 00h When bit 0 is 0 (meaning the I2C port is idle), SCLK (pin 71) will be tri-stated. Envy24 is providing the serial clock only when it reads/writes through I2C bus at a nominal rate of 31.25 KHz.
Bit
7 6:2 1 0
Attribute
RO 0 R/W RO
Description
Reflects the power strapping on GPIO3 (pin 53). A 1 (default) indicates external E2PROM exists. A 0 (pull down by a resistor) means, no external E2PROM connected. Reserved. Keep at 0 state. IC port read/write status. 0: idle 1: busy
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CCS14: Consumer Record DMA Current / Base Address Index: 14h - 17h Default Value: 00000000h:
Bit
31:28 27:0
Attribute
R0 R/W
Description
Write the Record DMA base address Read the current Record DMA count Byte aligned boundary is supported on this DMA channel.
CCS18: Consumer Record DMA Current / Base Count Index: 18h - 19h Default Value: 0000h
Bit
15:0
Attribute
R/W
Description
Write the Record DMA initial buffer size in bytes minus one. This register auto-decrements as the DMA transfer progresses. It reinitializes automatically to the original buffer size once it reaches 0 count. Read current Record DMA pointer.
See also registers CCI10 and CCI11 for Record DMA interrupt generation.
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CCS1B: PCI Configuration SERR# Shadow Address Offset: 1Bh Default Value: 00h
Bit
7:1 0
Attribute
R0 R/W
Description
Reserved. This bit shadows bit PCI04[8]. A 1 indicates SERR# assertion enabled, a 0 assertion disabled
CCS1C: Secondary MIDI UART Data Address Offset: 1Ch Default Value: 00h
Bit
7:0
Attribute
R/W
Description
MIDI UART data register
CCS1D: Secondary MIDI UART Command / Status Address Offset: 1Dh Default Value: 00h
Bit
7:0
Attribute
R/W
Description
MIDI UART command and status register
CCS1E: Timer Index: 1Eh - 1Fh Default Value: 4000h
Bit
15 14:0
Attribute
R/W R/W
Description
0: Timer count disable (default) 1: Timer count enable Read: the current timer value Write: to set up the period for the internal 15 bits timer to generate interrupt. This timer uses the internal MIDI logic clock (500 KHz).
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4.2 Controller Indexed Registers
The following section describes the content to be written to or read through CCS03 and CCS04 registers and their effect on the controllers operation. These 8-bit indexed registers manage various functions. It may take multiple accesses if a functionality control takes more than one 8-bit register. Registers CCI00 to CCI0F are defined for output through DMA Channel-E and Channel-F while CCI10 to CCI1F for the consumer section capture on Record DMA channel. See Table 4-2 in section 4.3 for the description of the DMA channels. CCI00: Playback Terminal Count (High Byte) Index: 00h Default Value: 00h
Bit
7:0
Attribute
WO
Description
Write the high byte playback terminal count in bytes. This register auto-decrements as the DMA transfer progresses. When it reaches 0, it generates and interrupt. Program the desired count in dword units minus one to determine the interrupt frequency desired.
CCI01: Playback Terminal Count (Low Byte) Index: 01h Default Value: 00h
Bit
7:0
Attribute
WO
Description
Write the high byte playback terminal count in bytes. See description above in CCI00.
CCI02: Playback Control Index: 02h Default Value: 00h
Bit
7 6 5 4 3 2 1 0
Attribute
R/W R/W R0b R/W R/W R/W R/W R/W
Description
Turbo mode (4x up sampling in the host by software), valid only when sampling rate is at 12 KHz or above. When this bit is set to 1, the Channel E and F in DirectSound will accept the 4x up streams. Reserved 0: 16 bits signed 1: 8 bits unsigned 0: mono 1: stereo FIFO flush (sticky bit. Requires toggling). Pause Playback enable
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CCI03: Playback Left Volume / Pan Index: 03h Default Value: 07h
Bit
7:6 5:0
Attribute
R00b R/W
Description
Left stream volume: 1.5dB attenuation per step. Default: -10.5dB 000000: 0dB .... 000111 : 10.5 dB (default) .... 011111: -46.5dB 111111: muted (instead of -94.5dB)
CCI04: Playback Right Volume / Pan Index: 04h Default Value: 07h
Bit
7:6 5:0
Attribute
R00b R/W
Description
Right stream volume:1.5dB attenuation per step. Default: -10.5dB 000000: 0dB .... 000111 -10.5 dB (default) .... 011111: -46.5dB 111111: muted (instead of -94.5dB)
CCI05: Soft Volume / Mute Control Index: 05h Default Value: 05h (about 6.4ms from 0 to 96dB)
Bit
7:0
Attribute
R/W
Description
Soft volume update rate (48 KHz/[CCI05], about every 20 s*[CCI05] per 1.5dB step). These bits apply to all the DirectSound channels 0 through D as well.
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CCI06: Playback Sampling Rate (Low Byte) Index: 06h Default Value: 0xFFh
Bit
7:0
Attribute
R/W
Description
see note below.
Note: SR, consumer mode (WAV PCM on Channel E and F) Sampling Rate is a 20-bit value programmed among registers CCI06 through CCI08. SR = fs* 220/48000. This has the resolution of less than 1Hz. When it is programmed to (220 -1), sampling rate will be rounded to 48 KHz exactly.
CCI07: Playback Sampling Rate (Middle Byte) Index: 07h Default Value: 0xFFh
Bit
7:0
Attribute
R/W
Description
see note under CCI06.
CCI08: Playback Sampling Rate (High Byte) Index: 08h Default Value: 0x0Fh
Bit
7:4 3:0
Attribute
R0h R/W
Description
see note under CCI06.
CCI10: Record Current / Base Terminal Count (High Byte) Index: 10h Default Value: 00h
Bit
7:0
Attribute
WO
Description
Write the high byte record terminal count in bytes. Like register CCS18, this register also auto-decrements as the DMA transfer progresses. When it reaches 0, it generates and interrupt. Program the desired count in dword units minus one to determine the interrupt frequency desired.
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CCI11: Record Current / Base Terminal Count (Low Byte) Index: 11h Default Value: 00h
Bit
7:0
Attribute
WO
Description
Write the low byte record terminal count in bytes. See description above in CCI10.
CCI12: Record Control Index: 12h Default Value: 00h
Bit
7 6:3 2 1 0
Attribute
R/W R0h R/W R/W R/W
Description
1: Digital return enable: (only for DMA Channel-10) The recorded signal will be the sum of CSDIN and SRC outputs. 0: 16-bit signed; 1: 8-bit unsigned 0: stereo; 1: mono 0: Record disable 1: Record enable
Conditions in native mode record DMA transfer: It is assumed that: * 16 bit mono: starting address is in 2X and byte count is 2X (i.e., multiples of 2) bytes -1 * 16 bit stereo: starting address is in 4X and byte count is 4X bytes -1 * 8 bit mono: starting address is in 1X and byte count is 1X bytes -1 * 8 bit stereo: starting address is in 2X and byte count is 2X bytes -1 Each time DMA stops, the lowest bytes of address and count/TC are all need to be programmed before it starts again. Consumer record only at 48 KHz when using AC'97 codecs, such as the VT1611 that do not incorporate VSR support. Use the VT1611A to support hardware native VSR.
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CCI20: GPIO Data Index: 20h Default Value: 00h The direction is set up in CCI22 the GPIO direction control register. These register bits can be writable only when the corresponding mask bit is zero in the mask register. Also, if the direction is output, it reads back the last data written. Some GPIO pins may be optionally configured for predefined functions. The use of these will depend upon board configuration as defined by the EPROM settings content. See PCI60 (32-bit) register description for more details.
Bit
7:0
Attribute
R/W
Description
GPIO data (Warning: GPIO pins may be shared with other functions)
CCI21: GPIO Write Mask Index: 21h Default Value: FFh
Bit
7:0
Attribute
R/W
Description
GPIO write mask 0: Corresponding CCI20 register bit can be written. 1: Can NOT be written.
CCI22: GPIO Direction Control Index: 22h Default Value: 00h
Bit
7 6 5 4 3 2 1:0
Attribute
R/W R/W R/W R/W R/W R/W R/W
Description
GPIO7 direction. If 2nd MIDI UART in use, this bit will be read as 0 always. GPIO6 direction. If 2nd MIDI UART in use, this bit will be read as 1 always GPIO5 direction. If external clock synthesizer is used, this bit will be read as 1 always. GPIO4 direction. If external clock synthesizer is used, this bit will be read as 1 always. GPIO3 direction. During reset, this pin is used for EPROM power-on strapping. GPIO2 direction. If TESTEN# pin is active, this pin is always input. GPIO1 and GPIO0 direction control register.
For all bits 0: input; 1: output.
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CCI30: Consumer Section Power Down Index: 30h Default Value: 00h
Bit
7 6 5 4 3 2 1 0
Attribute
R/W R/W R/W R/W R/W R/W R/W R/W
Description
1: Crystal clock generation power down for XTAL_1 1: Game port analog power down Reserved. 1: Stop IC port clock 1: Stop MIDI clock 1: Stop AC'97 clock 1: Stop DS Block clock 1: Stop PCI clock for SB, DMA controller (excluding PCI BIU, config. space and this register)
CCI31: Multi-Track Section Power Down Index: 31h Default Value: 00h
Bit
7 6:3 2 1 0
Attribute
R/W R/W R/W R/W R/W
Description
1: Crystal clock generation power down for XTAL_2 Reserved 1: Stop S/PDIF clock 1: Stop Professional digital mixer clock 1: Stop Multi-track IS serial interface clock
There are four power states defined in the PCI bus power management spec.
States
D0 D1 D2 D3(hot)
Description
Normal operation state after system power up or internal reset not supported. Power down all the blocks defined in the power down registers. Same as D2 state, except a transition to D0 will generate an internal reset (incl. PCI config. space)
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4.3 DDMA Registers
The following register definitions are derived from the DDMA spec. They are used by the SoundBlaster legacy block (playback or record) Microsoft Windows MMSystem Wave (WAV) playback, also known as native mode. The following registers are offset from the base address set by PCI14 and described below by the [PCI14] symbol to reflect the DDMA base address.
I/O Address
[PCI14] + 0h [PCI14] + 1h [PCI14] + 2h [PCI14] + 3h [PCI14] + 4h [PCI14] + 5h [PCI14] + 6h [PCI14] + 7h [PCI14] + 8h [PCI14] + 9h [PCI14] + Ah [PCI14] + Bh [PCI14] + Ch [PCI14] + Dh [PCI14] + Eh [PCI14] + Fh
Attribute
R/W R/W R/W R/W R/W R/W R/W W W W
Description
DMA Base and Current Address bit 0-7 DMA Base and Current Address 8 : 15 DMA Base and Current Address 16 :23 DMA Base and Current Address 24 : 31 DMA Base and Current Count 0 : 7 DMA Base and Current Count 8 :15 DMA Base and Current Count 16 : 23 (Not supported, reflecting the 64K page boundary) Reserved Status and Command Request. Not implemented. Reserved Mode Master reset Master clear. Not implemented. Reserved Channel Mask
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4.4 DMA Path Descriptions
Physically, there are 19 individual bus master DMAs, 17 for playback and 2 for record. DMA Channels 0 to F are for the Consumer section (both native/SoundBlaster and DirectSound streams playback) as described in 4.4. Record DMA is used for native 48 KHz record. Both of consumer playback and record paths are interfaced to an external AC'97 compliant codec via AC-link. Channel-10 is used for transferring 10 individual data streams (e.g., 8 multi-track playback and one stereo S/PDIF) to 24-bit outputs. The relevant register descriptions can be found in section 4.5. These 10 streams are sent from the system memory in interleaved data format through one DMA FIFO/address/count/control register set only. Channel-11 is used for transferring 12 individual data streams (e.g. one stereo pair returned from the professional digital mixer, 8 professional multi-track record and one stereo S/PDIF input). These 12 streams are sent to the system memory in interleaved data format through one DMA FIFO/address/count/control register set only. Both of these playback/record channels can support externally IS type and AC'97 compliant codecs.
Table 4-3. DMA Channels and Respective Functionality
DMA Channels
Channel-0 Channel-1 Channel-2 Channel-3 Channel-4 Channel-5 Channel-6 Channel-7 Channel-8 Channel-9 Channel-A Channel-B Channel-C Channel-D Channel-E Channel-F Record DMA Channel-10 Channel-11
Cosumer/Multi-Track
DirectSound - 0 DirectSound - 1 DirectSound - 2 DirectSound - 3 DirectSound - 4 DirectSound - 5 DirectSound - 6 DirectSound - 7 DirectSound - 8 DirectSound - 9 DirectSound - A DirectSound - B DirectSound - C (FM/WT-L) DirectSound - D (FM/WT-R) DirectSound - E (PCM-L) DirectSound - F (PCM-R) SB/MMSYS PCM L/R Record Multi-track Playback (10 interleaved) Multi-track Record (12 interleaved)
Direction
O O O O O O O O O O O O O O O O I O I
Destination/Source
CSDOUT: L/R CSDOUT: L/R CSDOUT: L/R CSDOUT: L/R CSDOUT: L/R CSDOUT: L/R CSDOUT: L/R CSDOUT: L/R CSDOUT: L/R CSDOUT: L/R CSDOUT: L/R CSDOUT: L/R CSDOUT: L CSDOUT: R CSDOUT: L CSDOUT: R CSDIN: L/R PSDOUT0-3 L/R and SPDOUT PSDIN0-3 L/R, SPDIN and digital mix
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4.5 Consumer Section DMA Channel Registers
The following registers are offset from base address set by PCI18. The DSx registers are located at [PCI18]+x. The 16 bytes I/O space controls the consumer section DMA channels for DOS legacy, native and DirectSound. Table 4-4. DSx Consumer DMA Channel Register Map
Byte 3
DirectSound DMA Interrupt Status Channel Data Channel Index
Byte 2
Byte 1
DirectSound DMA Interrupt Mask
Byte 0
Offset (Hex)
00 04 08 0C
DS0: DirectSound DMA Interrupt Mask Address Offset: 00 - 01h Default Value: 3FFFh
Bit
15:14 13:00
Attribute
R00b R/W
Description
Each bit corresponding to the interrupt mask for each channel (0 to D). Default is masked.
DS2: DirectSound DMA Interrupt Status Address Offset: 02 - 03h Default Value: 0000h
Bit
15:14 13:0
Attribute
R00b R/WC/
Description
Each bit corresponding to the interrupt status of each channel (0 to D) These are sticky bits. The driver needs to clear by writing a 1 to the corresponding bit.
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DS4: Channel Data Address Offset: 04h - 07h Default Value: 00000000h.
Bit
31:0
Attribute
R/W
Description
Channel Data register. See 32-bit index register description after Table
4-5.
DS8: Channel Index Address Offset: 08h Default Value: 00h
Bit
7:4 3:0
Attribute
R/W R/W
Description
Channel number. Valid only from Channel-0 to D. E and F are reserved for PCM streams regardless whether running in native or SB mode. Channel Index register. The table below is used for command decoding purposes.
Table 4-5. DS8 Register, Low Nibble Index Description Applicable to Channel-0 through D
Index
0h
Attribute
R/W
Description
Bits [27:0] W: Buffer_0 DMA base address[27:0] R: current active DMA buffer address[27:0]. Byte address. Bits [15:0] W: Buffer_0 DMA base count [15:0] R: current active DMA count [15:0]. Program byte count minus one. Bits[27:0] W: Buffer_1 DMA base address bit [27:0] R: same as in index 0h. Byte address Bits [15:0] W: Buffer_1 DMA base count [15:0] R: same as in index 1h. Program byte count minus one. Bits [7:0] R/W: Channel Control and Status register. Bits [19:0] Channel Sampling Rate Bits [13:0] (see note below) Channel left and right volume/pan control
1h
R/W
2h
R/W
3h
R/W
4h 5h 6h
R/W R/W R/W
Note:
* When the playback enable bit is changed from 0 to 1 (in Index 4 bit 0), the first active buffer will be from buffer 0. Before this, the return active address and count will not be updated. Conditions in DMA transfer: * * * * 16 bit mono: starting address is in 2X and count is multiple of 2X bytes (-1) 16 bit stereo: starting address is in 4X and count is multiple of 4X bytes (-1) 8 bit mono: starting address is in 1X and count is multiple of 1X bytes (-1) 8 bit stereo: starting address is in 2X and count is multiple of 2X bytes (-1)
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Channel Control and Status at Index 4h (DS8 = x4h) Default: 00000060h
Bit
31:8 7
Attribute
R000h RO
Description
1: indicating that the current active buffer is Buffer_1. 0: indicating that the current active buffer is Buffer_0. To avoid the case of reading this bit during the transition, it is recommended that driver read this bit in the ISR so that the returned address and count are in-sync. with the buffer status. 0: Buffer_1 auto init. disable (single block mode) 1: Buffer_1 auto init. enable (loop mode), default. 0: Buffer_0 auto init. disable (single block mode) 1: Buffer_0 auto init. enable (loop mode ), default. Flush FIFO 1: stereo; 0: mono (default). For the DirectSound path this bit is only valid and can be programmed in the even number of channels, i.e., 0,2,4..,C. The second data element will be routed to the next odd slot into the internal SRC core. Driver should not program the odd number channel address and count etc. since it is occupied. (sampling rate and volume should still be programmed, however). Consumer mode data format: 0: 16-bit signed; 1: 8-bit unsigned DMA request 1:pause DMA request 1: start, 0:stop
6 5 4 3
R/W R/W R/W R/W
2 1 0
RW RW RW
Consumer Mode Sampling Rate at Index 5h (DS8 = x5h) Index: 05h Default Value: 0x000FFFFFh (48 KHz)
Bit
31:20 19:00
Attribute
R0 R/W
Description
SR: Sampling Rate for all DirectSound streams (except Channel E and F, see CCI06) is a 20-bit value. SR = fs* 220/48000. This has the resolution of less than 1Hz. When it is programmed to (220 -1), sampling rate will be rounded to 48 KHz exactly.
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Consumer Mode Left / Right Volume at Index 06h (DS8 = x6h) Index: 06h Default: 00000707h
Bit
31:14 13:8
Attribute
R0 R/W
Description
Right volume:1.5dB attenuation per step. 000000: 0dB .... 000111: -10.5 dB (default) .... 011111: -46.5dB .... 111111: muted (instead of -94.5dB) Left volume :1.5dB attenuation per step. Default: -10.5dB. Same table as in Right volume.
7:6 5:0
R0 R/W
Note:
Channels E and F are dedicated for consumer PCM left and right streams respectively for either Microsoft Windows MMSystem Wave (WAV) or SoundBlaster. In the MMSystem mode, the sampling rate and the volume are defined in the CCS3 and CCS4 index registers. In the SB mode, the sampling rate is coming from SB command and volume is defined in the SB mixer registers. Channel C and D are dedicated for FM synthesis output left and right streams respectively in the SB mode. In this case, the FM volume will be coming from the SB mixer register space setting. The sampling rate, however, is determined from the above DS8 index registers. Table 4-6. Channel Parameter Controls
Channels
E:F C:D C:D E:F C:D
Mode
Legacy Legacy Legacy Native Native
Data
DOS SB PCM DOS FM DOS WT Native PCM Native FM/WT
Interrupt Status Bit
INTA# (routing) NMI: for I/O trapping INTA# or NMI for data transfer Same as above INTA#: CCS02 INTA#: DS2, DS3
Volume Control
SB mixer register SB mixer register DS8=x6h CCS00[4]=1b CCS03, CCS04 DS8, index register 6
Sampling Frequency
SB command DS8, index register 5 Programmed by TSR Same as above. SE index registers 6-8 DS8, index register 5
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4.6 Professional Multi-Track Control Registers
The following registers are offset from base address set by PCI1C. The MTxx registers are located at [PCI1C]+xx. The 64 bytes I/O space controls the professional multi-track record and playback, audio stream routing, digital mixer and related output capability. Refer to Table 4-3 on page 19 of this chapter for a concise description of the DMA channels involved. Table 4-7. MTxx Controller Register Map
Byte 3
-
Byte 2
IS data format
Byte 1
Sampling Rate Select. P. AC `97 Comm./Stat.
Byte 0
DMA Int. Mask/Status Prof. AC `97 Index
Offset (Hex)
00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34
Professional section AC `97 Data Port
Professional Playback DMA Current/Base Address P. Playback DMA Current/Base Terminal Count Professional Record DMA Current/Base Address P. Record DMA Current/Base Terminal Count Routing control to SPDOUT Routing control to PSDOUT[3:0] Prof. Record DMA Current/Base Count P. Record Control Prof. Playback DMA Current/Base Count P. Playback Control
Captured data Routing Selection Volume Control Rate Peak meter data Vol. Control Ch. Index Peak meter index L/R Volume Control Mixer monitor return
38 3C
4.6.1 Multi-Track Mode Control Registers
MT00: Professional Section DMA Interrupt Mask and Status Address Offset: 00h Default Value: C0h This register relates to both Channel-10 and 11 (Professional playback and record). When DMAs are stopped, the last latched value is retained. This "DC" value may affect the digital mixer operation.
Bit
7 6 5:2 1 0
Attribute
R/W R/W R0 R/W/C R/W/C
Description
Multi-track record interrupt mask Multi-track playback interrupt mask Multi-track record interrupt status. Write a 1 to clear. Multi-track playback interrupt status. Write a 1 to clear.
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MT01: Professional Section Sampling Rate Select Address Offset: 01h Default Value: 00h. This register applies to both Channel-10 and 11. For S/PDIF input, correct sampling rate must be set as well. See Figure 4-4-3 and Figure 4-4-4 on page 27 and page 28 respectively, in this chapter.
Bit
7:5 4
Attribute
R000b R/W
Description
S/PDIF input clock as the master. 0: disabled 1: enabled. S/PDIF receiver chip provides the master clock through SPMCLKIN (pin 111) Note that in this mode, 256X is the highest master clock available while the AC'97 MCLK requires 512X. VIA Technologies' AC'97 codecs, such as the VT1611, are designs based on BCLK which uses MCLK/2, i.e. 256X. When S/PDIF provides the master clock, if VIA Technologies' AC'97 codecs are used, before setting S/PDIF as the master clock, proceed to switching the primary codec into slave mode (refer to the VT1611 datasheet). In this mode PBCLK will be output from Envy24. Codec sampling rate select: All multi-track channels are set to the same rate. These bits are ignored if S/PDIF input is master. 0000: 48 KHz 0001: 24 KHz 0010: 12 KHz 0011: 9.6 KHz 0100: 32 KHz 0101: 16 KHz 0110: 8 KHz 0111: 96 KHz 1111: 64 KHz 1000: 44.1 KHz 1001: 22.05 KHz 1010: 11.025 KHz 1011: 88.2 KHz others: reserved
3:0
R/W
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MT02: Professional Section AC'97 Codec IS Data Format Address Offset: 02h Default Value: 00h
Bit
7:4 3
Attribute
R0 R/W
Description
MCLK/LRCLK ratio, 0: 256x (default) 1: 128x SCLK/LRCLK ratio, i.e. bpf (bits per frame, each frame corresponding to 1/SR) Typically useful for 44.1 KHz sampling rate and its multiples where converters use 384X oversampling. If S/PDIF is used as reflected in PCI63[0] or 1, 64bpf mode is forced and this bit is rendered inactive. 0: 64bpf (32/32) default. (PMCLK on pin 85 is 256 * LRCLK) 1: 48bpf (24/24) (PMCLK is 384 * LRCLK) Data format: 00: IS (timing diagram provided below) others: Reserved
2
R/W
1:0
R/W
See Figure 4-4-2 below for a timing diagram for bits [1:0]. See Figure 4-4-3 and Figure 4-4-4 on page 27 and page 28 respectively for the visual description of other bits.
PSYNC/ SPSYNC PBCLK/ SPSCLK PSDIN[0:3] PSDOUT[0:3] SPDIN SPDOUT
Left
Right
MSB
LSB
MSB
LSB
MSB
Figure 4-2. IS Format Timing Diagram MT04: Professional Section AC'97 Codec Index Address Offset: 04h Default Value: 00h
Bit
7 6:0
Attribute
R0 R/W
Description
AC'97 registers Index. Refer to the AC'97 specification for register descriptions.
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CMCLK (pin 92) 512fsc 1 2
CBCLK (pin 90) 256fsc SP* = S/PDIF IS port CSYNC (pin 88) fsc SCLK (pin 71)
Figure 4-3. Crystals to Master Clocks Clock Generation Tree
1 256
C* = Consumer section P* = Pro section fsp = Pro sampling rate fsc = Consumer sampling rate
1 49152 MPU-401 and Game Port logic
1 8
1 2
MIDI TX/RX rate
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XIN1 (pin 64)
divide by
1, 2, 3, 4, 6, 8, 10, 12 MT01[3:0]
256X
MT02[3]=0
1 2 1 3
MT02[3]=1 PCI60[7:6]=01 & PCI63[1:0]=00
Master
XIN2 (pin 60)
MT01[4]=0
divide by
1, 2, 4, 8 for 384X and SPDIF absent
PMCLK (pin 85)
SPMCLKIN (pin 111) 256fsp
MT01[4]=1
Slave
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Figure 4-4. Master Clocks to Bit Clocks, L/R Clocks and Sync Generation
MT01[4] = 1 & PCI61[7] = 0
1 2
PBCLK (pin 78)
MT02[2] = 1 & PCI63[1:0] = 00b
for 384X and SPDIF absent
1 48 default (256X or 128X)
MT02[3] = 1 & PCI61[7] = 1 (MT02[3] = 0 or PCI60[6] = 0) & PCI61[7] = 1
PMCLK (pin 85)
MT02[2] = 0
1 4
1 64
PSYNC (pin 72) fsp
MT02[3] = 1 & PCI61[7] = 1 MT02[3] = 1
1 2
1 8
PCI61[7] = 0
1 256 for AC'97 mode only
VT1712 - PCI Multi-Channel Audio Controller
128X MCLK
MT01[4] = 1 or MT02[3] = 0
1 4
default 256X MCLK or SPDIF in master
1 2
1 64
SPSYNC (pin 109) fsp SP* = S/PDIF IS port P* = Pro section fsp = Pro sampling rate
for AC'97 mode only SPMCLKOUT (pin 112) 128fsp SPSCLK (pin 110) 64fsp
PCI61[7] = 0
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MT05: Professional Section AC'97 Codec Command / Status Address Offset: 05h Default Value: 00h
Bit
7 6
Attribute
R/W R/W
Description
Cold reset. Write 1 to assert PRST# (pin105) active. Write back 0 to remove reset condition from all professional section codecs. Warm reset. Write 1 to have warm reset by asserting PSYNC (pin 72). This bit together with PRST# (pin 105) active (MT05[7]=1) can be used to set the external VIA Technologies' primary AC'97 codec to slave mode (such as the VT1611). This must be done when S/PDIF input is the master. Apply Cold reset to restore codec master mode. Write 1 to write to AC'97 codec register Reading a 1 indicates the write cycle is still in progress, cleared when write cycle complete. Write 1 to read AC'97 CODEC register Reading a 1 indicates the read cycle is still in progress, cleared when there is valid data. AC'97 codec ready status bit. After power-on, check that this bit is 1 before accessing codec registers. ID for external AC'97 registers read/write. 00: select primary AC'97 codec. 01: select second slave AC'97 codec. 10: select third slave AC'97 codec. 11: select fourth slave AC'97 codec.
5 4 3 2 1:0
R/W R/W RO R0b R/W
MT06: Professional Section AC'97 Codec Data Port Address Offset: 06h - 07h Default Value: 00h
Bit
15:8 7:0
Attribute
R/W R/W
Description
AC'97 codec register data high byte (index 07h) Refer to the AC'97 specification for register descriptions.. AC'97 codec register data low byte (index 06h). Refer to the AC'97 specification for register descriptions.
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4.6.2 Multi-Track Playback Registers The following figure is a visual representation of the multi-track data transfer mechanism. A ping-pong buffer structure is implemented for a seamless flow of multiple streams. 32-bit data transfers are used regardless of the audio data resolution. All transfer data are left (MSB) justified. Each transfer request results into a PCI bus master burst cycle.
from physical inputs to physical outputs
Stream/Track Stream/Track 1 2 3 4 5 6 7 8 9 10
Byte Lanes
3
2
1
0 (Playback)
3
2
1
0 (Record)
12 11 10 9 8 7 6 5 4 3 2 1
DMA Channel-10
DMA Channel-11
PCI
Figure 4-5. Multi-Track DMA Transfer
MT10: Professional Section Playback DMA Current / Base Address Index: 10h - 13h Default Value: 00000000h. Channel-10 interleaves 10 slots, each with 32-bit from the system memory.
Bit
31:28 27:2
Attribute
R0h R/W
Description
- (Address space beyond 256MB is not supported) Write the Playback DMA base address in dword units (up to 256 MB address space supported) Read current address in dword units. - (This DMA channel supports dword boundary only)
1:0
R00b
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MT14: Professional Section Playback DMA Current / Base Count Index: 14h - 15h Default Value: 0000h
Bit
15:0
Attribute
R/W
Description
Write the Playback DMA initial buffer size in dword units minus one. This register auto-decrements as the DMA transfer progresses. It reinitializes automatically to the original buffer size once it reaches 0 count. Read the current Playback DMA pointer.
MT16: Professional Section Playback Current / Base Terminal Count Index: 16 - 17h Default Value: 0000h
Bit
15:0
Attribute
WO
Description
Write the terminal count. This register also auto-decrements as the DMA transfer progresses. When it reaches 0, it generates and interrupt. Program the desired count in dword units minus one to determine the interrupt frequency desired.
MT18: Professional Section Playback and Record Control Index: 18h Default Value: 00h.
Bit
7:3 2 1 0
Attribute
R0 R/W R/W R/W
Description
1: Record start; 0: Record stop. Shadowed in MT28[0]. 1: Pause; 0: Resume 1: Playback start; 0: Playback stop
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4.6.3 Multi-Track Record Registers
MT20: Professional Section Record DMA Current / Base Address Index: 20h - 23h Default Value: 00000000h. Channel-11 interleaves 12 slots, each with 32-bit data to the system memory.
Bit
31:28 27:2
Attribute
R0h R/W
Description
- (Address space beyond 256MB is not supported) Write the Playback DMA base address in dword units (up to 256 MB address space supported) Read current address in dword units. - (This DMA channel supports dword boundary only)
1:0
R00b
MT24: Professional Section Record DMA Current / Base Count Index: 24 - 25h Default Value: 0000h
Bit
15:0
Attribute
R/W
Description
Write the Record DMA initial buffer size in dword units minus one. This register auto-decrements as the DMA transfer progresses. It reinitializes automatically to the original buffer size once it reaches 0 count. Read the current Record DMA pointer after having allowed at least 2 sample frames.
MT26: Professional Section Record Current / Base Terminal Count Index: 26h - 27h Default Value: 0000h
Bit
15:0
Attribute
WO
Description
Write the terminal count. This register also auto-decrements as the DMA transfer progresses. When it reaches 0, it generates and interrupt. Program the desired count in dword units minus one to determine the interrupt frequency desired.
MT28: Professional Section Record Control Index: 28h Default Value: 00h
Bit
7:1 0
Attribute
R0 R/W
Description
1: Record start; 0: Record stop. Same functionality as MT18[2]
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4.6.4 Professional Section Digital Loopback
The Envy24 provides an extensive routing capability of the data streams. The following registers control the routing from numerous sources to various destination. Insertion of the stream routing functionality adds a maximum of a single sample cycle delay with respect to the original data. The switch matrix being so complex, careful register setting is crucial to avoid undesirable effects. For simplicity of the register description only pin names are used. Refer to the pin list for pin numbers and location. The diagram below is a visual representation of possible connection. If a dot is missing on an intersection, it reflects the lack of routing capabitlity.
Destination
Consumer L Consumer R
Output to DAC
Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 Stream 8 Stream 9 Stream10
Input to DMA
Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot10 Slot11 Slot12
Output from DMA Input from ADC
Source
Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot10 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 Stream 8 Stream 9 Stream10 D mix L D mix R
Figure 4-6. Data Stream Routing Capabilities
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MT30: Routing Control for Data to PSDOUT[0:3] Address Offset: 30h - 31h Default Value: 00h When PSDIN[0:3] or SPDIN are selected as the source, refer to register MT34.
Bit
15:14
Attribute
R/W
Description
PSDOUT[3] Right source 00: from DMA Channel-10 output slot 8 01: 10: from PSDIN[X] loopback 11: from SPDIN input loopback PSDOUT[2] Right source 00: from DMA Channel-10 output slot 6 01: 10: from PSDIN[X] loopback 11: from SPDIN input loopback PSDOUT[1] Right source 00: from DMA Channel-10 output slot 4 01: 10: from PSDIN[X] loopback 11: from SPDIN input loopback PSDOUT[0] Right source 00: from DMA Channel-10 output slot 2. 01: from digital mixer monitor Right output 10: from PSDIN[X] loopback 11: from SPDIN input loopback PSDOUT[3] Left source 00: from DMA Channel-10 output slot 7 01: 10: from PSDIN[X] loopback 11: from SPDIN input loopback PSDOUT[2] Left source 00: from DMA Channel-10 output slot 5 01: 10: from PSDIN[X] loopback 11: from SPDIN input loopback PSDOUT[1] Left source 00: from DMA Channel-10 output slot 3 01: 10: from PSDIN[X] loopback 11: from SPDIN input loopback PSDOUT[0] Left source 00: from DMA Channel-10 output slot 1 01: from digital mixer monitor Left output 10: from PSDIN[X] loopback 11: from SPDIN input loopback
13:12
R/W
11:10
R/W
9:8
R/W
7:6
R/W
5:4
R/W
3:2
R/W
1:0
R/W
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MT32: Routing Control for SPDOUT Address Offset: 32h - 33h Default Value: 0000h When PSDIN[0:3] or SPDIN are selected as the source, refer to register 38h-3Bh.
Bit
15
Attribute
R/W
Description
SPDIN input loop back to SPDOUT Right output 1: SPDIN Right input 0: SPDIN Left input PSDIN[X] input loop back to SPDOUT Right output 000: PSDIN[0]: L 001: PSDIN[0]: R 010: PSDIN[1]: L 011: PSDIN[1]: R 100: PSDIN[2]: L 101: PSDIN[2]: R 110: PSDIN[3]: L 111: PSDIN[3]: R SPDIN input loop back to SPDOUT Left output 1: S/PDIF right input 0: S/PDIF left input PSDIN[X] input loop back to SPDIOUT Left output 000: PSDIN[0]: L 001: PSDIN[0]: R 010: PSDIN[1]: L 011: PSDIN[1]: R 100: PSDIN[2]: L 101: PSDIN[2]: R 110: PSDIN[3]: L 111: PSDIN[3]: R Source loop back to the SPDOUT Right output 00: from DMA Channel-10 slot 10 01: from digital mixer monitor Right output 10: from PSDIN[X] (defined in bits 14:12 of this register) 11: from SPDIN (defined in bit 15 of this register) Source loop back to the SPDOUT Left output 00: from DMA Channel-10 slot 9 01: from digital mixer monitor Left output 10: from PSDIN[X] (defined in bits 10:8 of this register) 11: from SPDIN (defined in bit 11 of this register)
14 : 12
R/W
11
RW
10:8
RW
7:4 3:2
R0h R/W
1:0
R/W
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MT34: Captured (Recorded) Data Routing Selection Address Offset: 34 - 37h Default Value: 00000000h.
Bit
31
Attribute
R/W
Description
SPDIN input loopback to PSDOUT[3] Right slot 1: SPDIN Right input 0: SPDIN Left input PSDIN[X] loopback to PSDOUT[3] Right slot 000: PSDIN[0]: L 001: PSDIN[0]: R 010: PSDIN[1]: L 011: PSDIN[1]: R 100: PSDIN[2]: L 101: PSDIN[2]: R 110: PSDIN[3]: L 111: PSDIN[3]: R SPDIN input loopback to PSDOUT[3] Left slot 1: SPDIN Right input 0: SPDIN Left input PSDIN[X] loopback to PSDOUT[3] Left slot 000: PSDIN[0]: L 001: PSDIN[0]: R 010: PSDIN[1]: L 011: PSDIN[1]: R 100: PSDIN[2]: L 101: PSDIN[2]: R 110: PSDIN[3]: L 111: PSDIN[3]: R SPDIN input loopback to PSDOUT[2] Right slot 1: SPDIN Right input 0: SPDIN Left input PSDIN[X] loopback to PSDOUT[2] Right slot 000: PSDIN[0]: L 001: PSDIN[0]: R 010: PSDIN[1]: L 011: PSDIN[1]: R 100: PSDIN[2]: L 101: PSDIN[2]: R 110: PSDIN[3]: L 111: PSDIN[3]: R SPDIN input loopback to PSDOUT[2] Left slot 1: S/PDIF right input 0: S/PDIF left input
30:28
R/W
27
R/W
26:24
R/W
23
R/W
22:20
R/W
19
R/W
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Description
PSDIN[X] loopback to PSDOUT[2] Left slot 000: PSDIN[0]: L 001: PSDIN[0]: R 010: PSDIN[1]: L 011: PSDIN[1]: R 100: PSDIN[2]: L 101: PSDIN[2]: R 110: PSDIN[3]: L 111: PSDIN[3]: R SPDIN input loopback to PSDOUT[1] Right slot 1: SPDIN Right input 0: SPDIN Left input PSDIN[X] loopback to PSDOUT[1] Right slot 000: PSDIN[0]: L 001: PSDIN[0]: R 010: PSDIN[1]: L 011: PSDIN[1]: R 100: PSDIN[2]: L 101: PSDIN[2]: R 110: PSDIN[3]: L 111: PSDIN[3]: R PSDIN[X] loopback to PSDOUT[1] Left slot 1: S/PDIF right input 0: S/PDIF left input PSDIN[X] loopback to PSDOUT[1] Left slot. 000: PSDIN[0]: L 001: PSDIN[0]: R 010: PSDIN[1]: L 011: PSDIN[1]: R 100: PSDIN[2]: L 101: PSDIN[2]: R 110: PSDIN[3]: L 111: PSDIN[3]: R SPDIN input loopback to PSDOUT[0] Right slot 1: SPDIN Right input 0: SPDIN Left input PSDIN[X] loopback to PSDOUT[0] Right slot 000: PSDIN[0]: L 001: PSDIN[0]: R 010: PSDIN[1]: L 011: PSDIN[1]: R 100: PSDIN[2]: L 101: PSDIN[2]: R 110: PSDIN[3]: L 111: PSDIN[3]: R SPDIN input loopback to PSDOUT[0] Left slot 1: SPDIN Right input 0: SPDIN Left input
Bit
18:16
Attribute
R/W
15
R/W
14 : 12
R/W
11
R/W
10:8
R/W
7
R/W
6:4
R/W
3
R/W
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Description
PSDIN[X] loopback to PSDOUT[0] Left slot 000: PSDIN[0]: L 001: PSDIN[0]: R 010: PSDIN[1]: L 011: PSDIN[1]: R 100: PSDIN[2]: L 101: PSDIN[2]: R 110: PSDIN[3]: L 111: PSDIN[3]: R
Bit
2:0
Attribute
R/W
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4.6.5 Multi-Track Digital Monitoring
The Envy24 integrates a 36-bit resolution digital hardware mixer. The width of the data path is strictly to ensure that during processing of all the channels, under any condition, no resolution is lost. The dynamic range of the end user system will be limited by the range of the physical output devices used. In order to maintain identical gain to the input stream (i.e. 0dB), the resulting 24-bit is not msb-aligned to the 36-bit. The overflow bits correspond to the analog distortion due to saturation. The user would need to reduce the overall attenuation of the inputs to avoid clipping. Insertion of the digital mixer adds only a single sample cycle delay with respect to the original data. This extremely low latency all digital mixer provides monitoring functionality and can replace a traditional external analog input mixer. There are 20 independent audio data streams to mix and control the volume. The output destination of this mixer can be the consumer AC `97 codec, an external DAC at PSDOUT[0] or SPDOUT or both simultaneously, as well as return to the host on slots 11 and 12 (the last two) of DMA Channel-11. Refer to the registers MT30, MT32, MT34 and MT3Ch in section 4.5.4 about audio data routing. Note that the consumer AC'97 path is limited to 48 KHz sampling rate maximum and for sub-48 KHz sampling rates, Channel-A and B of the DirectSound accelerator are allocated for SRC when the digital mixer return stream is at a sample rate other than 48 KHz. All other DirectSound streams operate concurrently without alterations. MT38: Left / Right Volume Control Data Address Offset: 38 - 39h Default Value: 0707h Refer to MT3A register for the audio data channel selection.
Bits
15 14:8 7 6:0
Attribute
R0b R/W R0b R/W
Description
Right Volume control. Same format as the in the left volume control. Left volume control. 0000000: 0dB 0000001: -1.5dB (0.841395141) 0000010: -3.0dB (0.7079458) 0000011: -4.5dB (0.5956621) .... 0000111: -10.5 dB (default) .... 0011111: -46.5dB .... 0111111: -94.5dB 1000000: -96dB .... 1100000: -144dB (maximum attenuation) 1111111: mute
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MT3A: Volume Control Stream Index Address Offset: 3Ah Default Value: 00h
Bit
7:6 5:0
Attribute
R00b R/W
Description
Index to select stream: 00000: Playback stream 1 (Channel-10 slot 1) 00001: Playback stream 2 (Channel-10 slot 2) 00010: Playback stream 3 (Channel-10 slot 3) 00011: Playback stream 4 (Channel-10 slot 4) 00100: Playback stream 5 (Channel-10 slot 5) 00101: Playback stream 6 (Channel-10 slot 6) 00110: Playback stream 7 (Channel-10 slot 7) 00111: Playback stream 8 (Channel-10 slot 8) 01000: Playback stream 9 (Channel-10 slot 9, typ. S/PDIF Left output stream) 01001: Playback stream 10 (Channel-10 slot 10, typ. S/PDIF Right output stream) 01010: Record stream 1 (Channel-11 slot 1) 01011: Record stream 2 (Channel-11 slot 2) 01100: Record stream 3 (Channel-11 slot 3) 01101: Record stream 4 (Channel-11 slot 4) 01110: Record stream 5 (Channel-11 slot 5) 01111: Record stream 6 (Channel-11 slot 6) 10000: Record stream 7 (Channel-11 slot 7) 10001: Record stream 8 (Channel-11 slot 8) 10010: Record stream 9 (Channel-11 slot 9, typ. S/PDIF Left input stream) 10011: Record stream 10 (Channel-11 slot 10, typ. S/PDIF Right input stream) others: ignored.
MT3B: Volume Control Rate Address Offset: 3Bh Default Value: 30h
Bits
7:0
Attribute
R/W
Description
Volume update rate control (sampling rate, PSYNC)
This register allows gradual change of the digital mixer volume setting. The value in MT3B specifies the number of samples to elapse (in hex) between each 1.5dB increment/decrement in volume mixer. This gradual volume update continues until the setting programmed into MT38 is reached. The appropriate value to program may vary, but 00 or 01h are good choices for most cases.
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MT3C: Digital Mixer Monitor Routing Control Address Offset: 3Ch Default Value: 00h
Bits
7:6 0
Attribute
R0 R/W
Description
1: Route digital mixer output to the Consumer AC'97 path by allocating Channel-A and B.
Left Monitor Output (routing selection via MT30, MT32, MT3C) Peak 24b
Right Monitor Output (routing selection via MT30, MT32, MT3C) Peak 24b
Read peaks via MT3E, MT3F
36b
0dB 0dB 0dB
36b
0dB 0dB
36b
0dB 0dB
36b
0dB
MT38 ....
-144dB -144dB -144dB
MT38 ....
-144dB -144dB
MT39 ....
-144dB -144dB
MT39 ....
-144dB
24b Peak Peak Peak
24b Peak Peak
24b Peak Peak
24b Peak
slot 1..... slot 10slot 1..... slot 10 (Stream attenuator selection via MT3A) DMA Channel-10 DMA Channel-11 (Playback) (Record)
slot 1..... slot 10slot 1..... slot 10 (Stream attenuator selection via MT3A) DMA Channel-10 DMA Channel-11 (Playback) (Record)
Figure 4-7. Digital Mixer Functional Diagram
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MT3E: Peak Meter Index Address Offset: 3Eh Default Value: 00h
Bits
7:5 4:0
Attribute
R000b R/W
Description
Peak meter stream index 00000: Playback stream 1 (Channel-10 slot 1) 00001: Playback stream 2 (Channel-10 slot 2) 00010: Playback stream 3 (Channel-10 slot 3) 00011: Playback stream 4 (Channel-10 slot 4) 00100: Playback stream 5 (Channel-10 slot 5) 00101: Playback stream 6 (Channel-10 slot 6) 00110: Playback stream 7 (Channel-10 slot 7) 00111: Playback stream 8 (Channel-10 slot 8) 01000: Playback stream 9 (Channel-10 slot 9, typ. S/PDIF Left output stream) 01001: Playback stream 10 (Channel-10 slot 10, typ. S/PDIF Right output stream) 01010: Record stream 1 (Channel-11 slot 1) 01011: Record stream 2 (Channel-11 slot 2) 01100: Record stream 3 (Channel-11 slot 3) 01101: Record stream 4 (Channel-11 slot 4) 01110: Record stream 5 (Channel-11 slot 5) 01111: Record stream 6 (Channel-11 slot 6) 10000: Record stream 7 (Channel-11 slot 7) 10001: Record stream 8 (Channel-11 slot 8) 10010: Record stream 9 (Channel-11 slot 9, typ. S/PDIF Left input stream) 10011: Record stream 10 (Channel-11 slot 10, typ. S/PDIF Right input stream) 10100: Record stream 11 (Channel-11 slot 11, typ. digital mixer monitor Left output stream) 10101: Record stream 12 (Channel-11 slot 12, typ. digital mixer monitor Right output stream) others: ignored.
MT3F: Peak Meter Data Address Offset: 3Fh Default Value: 00h
Bits
7:0
Attribute
R
Description
Peak data derived from the absolute value of 9 msb. 00h min - FFh max volume. Reading the register resets the meter to 00h.
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Electrical Specifications
5.1 Maximum Ratings
Table 5-1. Maximum Ratings
Parameter
Storage Temperature Operating Ambient Temperature DC Supply Voltage (Analog and Digital) I/O Pin Voltage Power Dissipation
Min
-55 0 3.0 GND - 0.5
Typ
Max
150
Unit
C C V V W
25 3.3
70 4.0 VDD TBD
5.2 Electrical Specifications
Table 5-2. DC Characteristics
( TA=25C, VDD = 3.3V 5%; GND = 0V; 50pF Load )
Symbol
VIN VIL VIH VOL VOH - - -
Parameter
Input Voltage Range Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Leakage Current Output Leakage Current Output Buffer Drive Current
Min
-0.3
Typ
Max
VDD+0.3 0.3 x VDD
Unit
V V V
0.4 x VDD 0.2 x VDD 0.5 x VDD -10 -10 TBD 10 10
V V A A mA
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Table 5-3. Power Consumption
( TA=25C, VDD = 3.3V 5%; GND = 0V; 50pF Load )
Symbol
IVDD IVDD IVDD IVDD
Parameter
Supply Current: Power Up Supply Current: Partial Power Up Supply Current: Partial Power Down Supply Current: Power Down
Min
Typ
110 TBD TBD TBD
Max
Unit
mA mA mA mA
5.3 AC Timing Characteristics
(Test Conditions: TA=25C, VDD = 3.3V 5%; GND = 0V; 50pF Load)
Table 5-4. Cold Reset
Symbol
TRST_LOW TRST2CLK
Parameter
CRST#/PRST# Active Low Pulse Width CRST#/PRST# Startup Delay Inactive to CBLK/PBCLK/SPSCLK
Min
1 162.8
Typ
Max
Unit
s ns
TRST_LOW
xRST#
TRST2CLK
xxCLK
Figure 5-1. Cold Reset Timing
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Table 5-5. Warm Reset
Symbol
TSYNC_HIGH TSYNC2CLK
Parameter
CSYNC/PSYNC Active High Pulse Width CSYNC/PSYNC Inactive to CBLK/PBCLK Startup Delay
Min
Typ
1.3
Max
Unit
s ns
162.8
TSYNC_HIGH
xSYNC
TSYNC2CLK
xBCLK
Figure 5-2. Warm Reset Timing
Table 5-6. Slave Mode Master clock delay
Symbol
TSPI2MCK TSPI2SPO
Parameter
SPMCLKIN to PMCLK Delay SPMCLKIN to SPMCLKOUT Delay
Min
Typ
4 5.5
Max
Unit
ns ns
SPMCLKIN
TSPI2MCK
PMCLK SPMCLKOUT
TSPI2SPO Figure 5-3. Master Clock Delay
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Table 5-7. xBCLK / xxSYNC Timing
Symbol
xBCLK Frequency
TCLK_PERIOD
Parameter
xBCLK Period xBCLK Output Jitter xBCLK Pulse Width (high) xBCLK Pulse Width (low) xBCLK Duty Cycle xxSYNC Frequency
Min
Typ
see Appendix see Appendix TBD see Appendix see Appendix see Appendix see Appendix see Appendix see Appendix see Appendix
Max
Unit
MHz ns
750
ps ns ns % kHz s s s
TCLK_HIGH TCLK_LOW TCLK_DC
TSYNC_PERIOD xxSYNC Period TSYNC_HIGH TSYNC_LOW
xxSYNC Pulse Width (high) xxSYNC Pulse Width (low)
TCLK_HIGH
xBCLK
TCLK_LOW
TCLK_PERIOD TSYNC_HIGH
xxSYNC
TSYNC_LOW
TSYNC_PERIOD
Figure 5-4. xBCLK to xxSYNC Timing
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Table 5-8. Setup and Hold
Symbol
TSETUP1 THOLD1 TSETUP2 THOLD2
Parameter
xSDOUT Setup to falling edge of xBCLK xSDOUT Hold from falling edge of xBCLK xSYNC Setup to rising edge of xBCLK xSYNC Hold to rising edge of xBCLK
Min
15 5 15 5
Typ
Max
Unit
ns ns ns ns
Note:
SDATA_IN seup and hold calculations determined by AC'97 controller propagation delay.
TSETUP1
xBCLK xSDIN, xSDOUT xSYNC
THOLD1
TSETUP2 Figure 5-5. Setup and Hold Time
THOLD2
Table 5-9. Rise and Fall Time
Symbol
TRISE TFALL TRISE TFALL TRISE TFALL TRISE TFALL
Parameter
xBCLK rise time xBCLK fall time xxSYNC rise time xxSYNC fall time xSDIN rise time xSDIN fall time xSDOUT rise time xSDOUT fall time
Min
2 2 2 2 2 2 2 2
Typ
Max
6
Unit
ns ns ns ns ns ns ns ns
6
6 6 6 6 6 6
Revision 2.4, May 28, 2002
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Electrical Specifications
Technologies, Inc. We Connect
VT1712 - PCI Multi-Channel Audio Controller
BIT_CLK, SYNC
SDATA_IN, SDATA_OUT
TRISE
TFALL
Figure 5-6. Rise Time and Fall Time
Table 5-10. AC-Link Low Power Mode
Symbol
TS2_PDOWN
Parameter
End of Slot 2 to CBCLK/PBCLK to CSDIN/PSDIN low
Min
Typ
Max
1
Unit
s
Note:
CBCLK/PBCLK not to scale.
xSYNC
Slot 1
Slot 2
xBCLK
TS2_PDOWN
xSDOUT
xSDIN
Figure 5-7. AC-Link Power Mode Timing
Revision 2.4, May 28, 2002
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Electrical Specifications
Technologies, Inc. We Connect
VT1712 - PCI Multi-Channel Audio Controller
Mechanical Specifications
6.1 Thermal Specifications
Parameter
Thermal Resistenace JA (Still Air) Junction Temperature
Min
Typ
TBD TBD
Max
Unit
C/W C
Revision 2.4, May 28, 2002
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Mechanical Specifications
Technologies, Inc. We Connect
VT1712 - PCI Multi-Channel Audio Controller
6.2 Package Dimensions
A B
Pin 1 Identifier
DC
J E I H
F
G
Table 6-1. Mechanical Dimensions
Symbol
minimum
maximum
A
17.0 17.4
B
13.9 14.1
C
23.0 23.4
D
19.9 20.1
E
0 7
F
0.5
G
0.17 0.23
H
0.25 -
I
- 3.4
J
0.65 0.95
Note: Dimensions are in millimeters, unless otherwise stated.
Revision 2.4, May 28, 2002
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Mechanical Specifications
Technologies, Inc. We Connect
VT1712 - PCI Multi-Channel Audio Controller
Appendix A
A.1 Appendix A
The following tables will help system designers and software developers correctly set the sampling rate and clock ratios. To determine via software whether AC-link or IS converters are used, read back PCI61[7]. Based on the outcome either Table A-1 or Table A-2 should be used. To set the sampling rate, regardless of the converter type used, program MT01. MT02 will have no effect in AC-link mode. MT02 will set IS interface bpf, oversampling rate, master clock to sampling rate ratio and similar characteristics. For a visual description of hardware settings refer to Figure 4-4-3 and Figure 4-4-4 on page 27 and page 28 of chapter 4 respectively . Table A-1. AC-Link Interface Parameters and Ratios (Pin 50 Floating / Pulled Up)
PSYNC (SR in kHz)
96 48 24 12 32 16 8 9.6 44.1 22.05 11.025
PMCLK/PSYNC
512 512 512 512 512 512 512 512 512 512
XINx/PMCLK
1 2 4 1.5* 3* 6 5* 1 2 4
PBCLK / PSYNC (bpf)
256 256 256 256 256 256 256 256 256 256
Note: When using AC'97 codecs, the XIN2 must have 22.5792 MHz (512*44.1 KHz) to be able to support the sampling rates at 44.1 KHz and submultiples. The dividers marked with * at sampling rates 32 / 16 / 9.6 KHz, will not have 50% duty cycle PMCLK.
Table A-2. IS Interface Parameters and Ratios (Pin 50 Pulled Down)
PSYNC (SR in kHz)
96 64 48 24 12 32 16
PMCLK/PSYNC
128 or 256 128 128 or 256 128 or 256 128 or 256 128 or 256 128 or 256
XINx/PMCLK
2 or 1 3* 4 or 2 8 or 4 16 or 8 6 or 3* 12or 6
PBCLK / PSYNC (bpf)
64 64 64 64 64 64 64
Revision 2.4, May 28, 2002
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Appendix A
Technologies, Inc. We Connect
VT1712 - PCI Multi-Channel Audio Controller
Table A-2. IS Interface Parameters and Ratios (Pin 50 Pulled Down)
PSYNC (SR in kHz)
8 9.6 88.2 44.1 22.05 11.025
PMCLK/PSYNC
128 or 256 128 or 256 128 or 256 256 or 384 256 or 384 256 or 384
XINx/PMCLK
24 or 12 20 or 10 2 or 1 2 or 1 4 or 2 8 or 4
PBCLK / PSYNC (bpf)
64 64 64 64 or 48 64 or 48 64 or 48
Note: Clock source either 22.5792 MHz for 512*44.1 KHz or 16.9344 MHz for 384*44.1 KHz, software controlled via PCI60[7-6]. For 512*48 KHz, the clock source is 24.576 MHz. The divider marked with * like the one at 32 KHz sampling rate, will not have 50% duty cycle PMCLK. See MT02 for IS data format and clock ratios. 48 bpf is available for XIN2 originating clocks only.
Table A-3. S/PDIF Output IS Interface Parameters and Ratios
SPSYNC (SR in kHz)
96 48 44.1 32
SPMCLKOUT/SPSYNC SPSCLK/SPSYNC (bpf)
128 128 128 128 64 64 64 64
Note: Refer to CS8402A, CS8404A transmitters
Table A-4. S/PDIF Input IS Interface Parameters and Ratios
SPSYNC (SR in kHz)
96 48 44.1 32
SPMCLKIN/SPSYNC
256 256 256 256
SPSCLK/SPSYNC (bpf)
64 64 64 64
Note: Refer to CS8412, CS8414 receivers. To set the controller into slave mode, set MT01[4]. When S/PDIF input is the master clock, 256x is the maximum PMCLK. This input can be used to synchronize with external Super Word Clock inputs. This can also be used to slave multiple PCI controllers in a single workstation.
Revision 2.4, May 28, 2002
A-2
Appendix A

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